• Title/Summary/Keyword: contact etch

Search Result 62, Processing Time 0.029 seconds

The Improvement of Profile Tilt in High Aspect Ratio Contact (컨택 산화막 에칭에서의 바닥 모양 찌그러짐 변형 개선)

  • Hwang, Won-Tae;Choi, Sung-Gil;Kwon, Sang-Dong;Im, Jang-Bin;Jung, Sang-Sup;Park, Young-Wook
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2004.11a
    • /
    • pp.666-670
    • /
    • 2004
  • VLSI 소자에서 design rule(D/R)이 작아져 각 단위 Pattern의 size가 작아짐에 따라 aspect ratio가 커지게 되었다. 산화막 contact etch를 하는데 있어 산화막 측벽을 보호하는데, 이러한 보호막은 주로 fluoro-carbon 계열의 polymer precursor들이 사용된다. Aspect ratio(A/R)가 5 이하일 때에는 측벽의 보호막에 의한 바닥 변형이 문제가 되지 않으나, 10 이상의 A/R를 가진 contact에서는 크기가 줄고, 모양이 불균형하게 변하는 바닥 변형을 쉴게 관찰할 수 있다. 이러한 바닥 변형이 커지면 contact 저항이 높아지는 것은 물론이고, 심하게는 하부 pattern과 overlap 불량을 유발할 수 있다. 본 논문에서는 바닥변형을 일으키는 원인을 분석하고 fluoro-carbon 계열의 polymer precursor의 종류$(C_4_F6\;vs.\;C_3F_8)$에 따른 polymer증착 상태 확인 및 pattern비대칭에 따른 바닥 변형의 고찰과 plasma etching 시 H/W 변형을 통해 바닥 변형이 거의 없는 조건을 찾아낼 수 있었다.

  • PDF

A study on the optimal parameter design by analyzing the ordered categorical data (순차 범주형 데이타분석을 위한 최적모수설계에 관한 연구)

  • 전태준;홍남표;박호일
    • Proceedings of the Korean Operations and Management Science Society Conference
    • /
    • 1992.04b
    • /
    • pp.188-197
    • /
    • 1992
  • 제품 개발에 관한 응용 연구 혹은 개발 연구의 실험 결과가 품질특성의 본질적인 성격이나 측정시의 편의때문에 순차 범주형 자료(ordered categorical data)로 분류되는 경우가 있다. 본 논문에서는 망목 특성 문제(nominal-the-best type problem)를 분석하는데 있어서 기존의 다구찌 누적법이 순차 범주형 자료분석법이 안고 있는 문제점들을 고찰하고, 이를 개선하기 위해 품질손실에 근거한 목표 누적법을 제시한다. 본 논문에서 제시한 기법을 post-etch contact window데이타에 적용해 본 결과 인자의 최적수준을 결정하는데 용이하였다.

  • PDF

Co-firing Optimization of Crystalline Silicon Solar Cell Using Rapid Thermal Process (급속 열처리 공정을 이용한 결정질 실리콘 태양전지의 전극 소결 최적화)

  • Oh, Byoung-Jin;Yeo, In-Hwan;Lim, Dong-Gun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.25 no.3
    • /
    • pp.236-240
    • /
    • 2012
  • Limiting thermal exposure time using rapid thermal processing(RTP) has emerged as promising simplified process for manufacturing of solar cell in a continuous way. This paper reports the simplification of co-firing using RTP. Actual temperature profile for co-firing after screen printing is a key issue for high-quality metal-semiconductor contact. The plateau time during the firing process were varied at $450^{\circ}C$ for 10~16 sec. Glass frit in Ag paste etch anti-reflection layer with plateau time. Glass frit in Ag paste is important for the Ag/Si contact formation and performances of crystalline Si solar cell. We achieved 17.14% efficiency with optimum conditions.

Effects of Laser Doping on Selective Emitter Si Solar Cells (레이져를 이용한 도핑 특성과 선택적 도핑 에미터 실리콘 태양전지의 제작)

  • Park, Sungeun;Park, Hyomin;Nam, Junggyu;Yang, JungYup;Lee, Dongho;Min, Byoung Koun;Kim, Kyung Nam;Park, Se Jin;Lee, Hae-Seok;Kim, Donghwan;Kang, Yoonmook;Kim, Dongseop
    • Current Photovoltaic Research
    • /
    • v.4 no.2
    • /
    • pp.54-58
    • /
    • 2016
  • Laser-doped selective emitter process requires dopant source deposition, spin-on-glass, and is able to form selective emitter through SiNx layer by laser irradiation on desired locations. However, after laser doping process, the remaining dopant layer needs to be washed out. Laser-induced melting of pre-deposited impurity doping is a precise selective doping method minimizing addition of process steps. In this study, we introduce a novel scheme for fabricating highly efficient selective emitter solar cell by laser doping. During this process, laser induced damage induces front contact destabilization due to the hindrance of silver nucleation even though laser doping has a potential of commercialization with simple process concept. When the laser induced damage is effectively removed using solution etch back process, the disadvantage of laser doping was effectively removed. The devices fabricated using laser doping scheme power conversion efficiency was significantly improved about 1% abs. after removal the laser damages.

Ridge Formation by Dry-Etching of Pd and AlGaN/GaN Superlattice for the Fabrication of GaN Blue Laser Diodes

  • Kim, Jae-Gwan;Lee, Dong-Min;Park, Min-Ju;Hwang, Seong-Ju;Lee, Seong-Nam;Gwak, Jun-Seop;Lee, Ji-Myeon
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2012.02a
    • /
    • pp.391-392
    • /
    • 2012
  • In these days, the desire for the precise and tiny displays in mobile application has been increased strongly. Currently, laser displays ranging from large-size laser TV to mobile projectors, are commercially available or due to appear on the market [1]. In order to achieve a mobile projectors, the semiconductor laser diodes should be used as a laser source due to their size and weight. In this presentation, the continuous etch characteristics of Pd and AlGaN/GaN superlattice for the fabrication of blue laser diodes were investigated by using inductively coupled $CHF_3$ and $Cl_2$ -based plasma. The GaN laser diode samples were grown on the sapphire (0001) substrate using a metal organic chemical vapor deposition system. A Si-doped GaN layer was grown on the substrate, followed by growth of LD structures, including the active layers of InGaN/GaN quantum well and barriers layer, as shown in other literature [2], and the palladium was used as a p-type ohmic contact metal. The etch rate of AlGaN/GaN superlattice (2.5/2.5 nm for 100 periods) and n-GaN by using $Cl_2$ (90%)/Ar (10%) and $Cl_2$ (50%)/$CHF_3$ (50%) plasma chemistry, respectively. While when the $Cl_2$/Ar plasma were used, the etch rate of AlGaN/GaN superlattice shows a similar etch rate as that of n-GaN, the $Cl_2/CHF_3$ plasma shows decreased etch rate, compared with that of $Cl_2$/Ar plasma, especially for AlGaN/GaN superlattice. Furthermore, it was also found that the Pd which is deposited on top of the superlattice couldn't be etched with $Cl_2$/Ar plasma. It was indicating that the etching step should be separated into 2 steps for the Pd etching and the superlattice etching, respectively. The etched surface of stacked Pd/superlattice as a result of 2-step etching process including Pd etching ($Cl_2/CHF_3$) and SLs ($Cl_2$/Ar) etching, respectively. EDX results shows that the etched surface is a GaN waveguide free from the Al, indicating the SLs were fully removed by etching. Furthermore, the optical and electrical properties will be also investigated in this presentation. In summary, Pd/AlGaN/GaN SLs were successfully etched exploiting noble 2-step etching processes.

  • PDF

The Electrical and Radiation Detection Properties of $Au/Cd_{1-x}Zn_x/Te(x=20%)/Au$ Structure ($Au/Cd_{1-x}Zn_x/Te(x=20%)/Au$ 구조의 전기적 특성 및 방사선 탐지 특성)

  • 최명진;왕진석
    • Electrical & Electronic Materials
    • /
    • v.10 no.1
    • /
    • pp.39-44
    • /
    • 1997
  • Bulk type radiation detector of Au/Cd$_{1-x}$ Zn$_{x}$Te(x=20%)/Au structure using Cd$_{1-x}$ Zn$_{x}$Te(x=20%) wafer(3x4xl mm$^{3}$) grown by high pressure Bridgman method has been developed. We etched wafer surfaces with 2% Br-methanol solution and coated gold thin film on the surfaces by electroless deposition method for 5 min. in 49/o HAuCI$_{3}$ 4H20 solution. Initial etch rates of Cd, Zn and Te were 46%, 12% and 42% respectively. After etched, the surface of wafer was slightly revealed to Te rich condition. The leakage current was increased with etch time, but it didn't exceed 3nA at 50volt. The thickness of Au film was about 100nm by Rutherford Backscattering Spectroscopy(RBS). The resolution were 6.7% for 22.1 keV photon from 109 $^{109}$ Cd and 8.2% for 59.5 keV photon from $^{241}$ Am. The radiation detector such as Au/Cd$_{1-x}$ Zn$_{x}$Te(x=20%)/Au structure was more effective to monitor the low energy gamma radiation.iation.

  • PDF

3D feature profile simulation for nanoscale semiconductor plasma processing

  • Im, Yeon Ho
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2015.08a
    • /
    • pp.61.1-61.1
    • /
    • 2015
  • Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

  • PDF

Etch resist patterning of printed circuit board by ink jet printing technology (잉크젯 인쇄기술을 이용한 인쇄회로기판의 에칭 레지스터 패터닝)

  • Seo, Shang-Hoon;Lee, Ro-Woon;Kim, Yong-Sik;Kim, Tae-Gu;Park, Sung-Jun;Yun, Kwan-Soo;Park, Jae-Chan;Jeong, Kyoung-Jin;Joung, Jae-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.06a
    • /
    • pp.108-108
    • /
    • 2007
  • Inkjet printing is a non-contact and direct writing associated with a computer. In the industrial field, there have been many efforts to utilize the inkjet printing as a new way of manufacturing, especially for electronic devices. The etching resist used in this process is an organic polymer which becomes solidified when exposed to ultraviolet lights and has high viscosity of 300 cPs at ambient temperature. A piezoelectric-driven ink jet printhead is used to dispense $20-40\;{\mu}m$ diameter droplets onto the copper substrate to prevent subsequent etching. In this study, factors affecting the pattern formation such as printing resolution, jetting property, adhesion strength, etching and strip mechanism, UV pinning energy have been investigated. As a result, microscale Etch resist patterning of printed circuit board with tens of ${\mu}m$ high have been fabricated.

  • PDF

Study on Electrical Characteristics According Process Parameters of Field Plate for Optimizing SiC Shottky Barrier Diode

  • Hong, Young Sung;Kang, Ey Goo
    • Transactions on Electrical and Electronic Materials
    • /
    • v.18 no.4
    • /
    • pp.199-202
    • /
    • 2017
  • Silicon carbide (SiC) is being spotlighted as a next-generation power semiconductor material owing to the characteristic limitations of the existing silicon materials. SiC has a wider band gap, higher breakdown voltage, higher thermal conductivity, and higher saturation electron mobility than those of Si. When using this material to implement Schottky barrier diode (SBD) devices, SBD-state operation loss and switching loss can be greatly reduced as compared to that of traditional Si. However, actual SiC SBDs exhibit a lower dielectric breakdown voltage than the theoretical breakdown voltage that causes the electric field concentration, a phenomenon that occurs on the edge of the contact surface as in conventional power semiconductor devices. Therefore in order to obtain a high breakdown voltage, it is necessary to distribute the electric field concentration using the edge termination structure. In this paper, we designed an edge termination structure using a field plate structure through oxide etch angle control, and optimized the structure to obtain a high breakdown voltage. We designed the edge termination structure for a 650 V breakdown voltage using Sentaurus Workbench provided by IDEC. We conducted field plate experiments. under the following conditions: $15^{\circ}$, $30^{\circ}$, $45^{\circ}$, $60^{\circ}$, and $75^{\circ}$. The experimental results indicated that the oxide etch angle was $45^{\circ}$ when the breakdown voltage characteristics of the SiC SBD were optimized and a breakdown voltage of 681 V was obtained.

A Study on The Improvement of Profile Tilting or Bottom Distortion in HARC (높은 A/R의 콘택 산화막 에칭에서 바닥모양 변형 개선에 관한 연구)

  • Hwang, Won-Tae;Kim, Gli-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.18 no.5
    • /
    • pp.389-395
    • /
    • 2005
  • The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.