• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.12
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• pp.2298-2305
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• 1992

To obtain the convenient solution of the multibody dynamic systems composed of flexible beams, linear finite element technique is adopted and the nodal coordinates are interpolated in the global inertia frame. Mass matrix becomes an extremely simple constant matrix and the force vector also becomes extremely simple because Coriolis acceleration and centrifugal force are not required. And the elastic force is also simply computed from the moving frame attached to the material. To solve the global differential algebraic euation. an ODE technique is adopted after Lagrange multiplier is computed by the accelerated iterative technique, and the time demanding procedures such as Newton-Raphson iterations and decomposition of the big matrix are not required. The accuracy of the present solution is checked by a well-known example problem.

• ETRI Journal
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• v.33 no.5
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2039-2044
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• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of Power Electronics
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• v.10 no.3
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• pp.251-261
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• 2010

The general function of a multilevel converter is to synthesize a desired output voltage from several levels of dc voltages as inputs. In order to increase the steps in the output voltage, a new topology is recommended in [1], which benefits from a series connection of sub-multilevel converters. In the procedure described in this reference, despite all the advantages, it is not possible to produce all the steps (odd and even) in the output. In addition, for producing an output voltage with a constant number of steps, there are different configurations with a different number of components. In this paper, the optimal structures for this topology are investigated for various objectives such as minimum number of switches and dc voltage sources and minimum standing voltage on the switches for producing the maximum output voltage steps. Two new algorithms for determining the dc voltage sources magnitudes have been proposed. Finally, in order to verify the theoretical issues, simulation and experimental results for a 49-level converter with a maximum output voltage of 200V are presented.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.369-372
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• 2002

This paper presents a family of continuous conduction mode with constant-switching pulse width modulator controllers. Unified implementation of quasi steady state approach for various DC-DC converters topoiogies is illustrated. The property and control low for quasi-state approach will be discussed in this paper. The different procedures will be discussed in details with different results for five commonly used DC-DC converters. Both trailing and leading edge pulse width modulation are used. Leading edge modulation can some times lead to simpler control circuitry as will be demonstrated in some circuits. These controllers do not require the multiplier in the voltage feed back loop, error amplifier in the current loop and rectified line voltage sensor, which are needed by traditional control methods. Controller examples and design arc analyzed.

• Journal of Magnetics
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• v.16 no.2
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• pp.114-119
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• 2011

This paper presents a magnetization modeling method combined with material sensitivity information to identify the unknown magnetization distribution of a hull and improve the accuracy of the predicted fields. First, based on the magnetization modeling, the hull surface was divided into three-dimensional sheet elements, where the individual remanent magnetization was assumed to be constant. For a fast search of the optimum magnetization distribution on the hull, a material sensitivity formula containing the first-order gradient information of an objective function was combined with the magnetization modeling method. The feature of the proposed method is that it can provide a stable and accurate field solution, even in the vicinity of the hull. Finally, the validity of the method was tested using a scale model ship.

• ETRI Journal
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• v.19 no.4
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• pp.317-325
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• 1997

A new on-the-fly conversion algorithm is proposed, and high-speed array multipliers with the on-the-fly conversion are presented. The new on-the-fly conversion logic is used to speed up carry-propagate addition at the last stage of multiplication, and provides constant delay independent of the number of input bits. In this paper, the multiplication architecture and the on-the-fly conversion algorithm are presented and discussed in detail. The proposed architecture has multiplication time of (n +1)$t_{FA}$, Where n is the number of input bits and $t_{FA}$ is the delay of a full adder. According to our comparative performance evaluation, the proposed architecture has shorter delay and requires less area than the conventional array multiplier with on-the-fly conversion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of the Optical Society of Korea
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• v.8 no.1
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• pp.29-33
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• 2004

We propose and demonstrate a novel optical pulse multiplier applicable to OTDM (Optical Time Division Multiplexing) systems using cascaded long-period fiber gratings. We have exploited the fact that each mode in a fiber has a different propagation constant to obtain time delays among optical pulses. The proposed scheme could realize high-frequency optical pulse multiplication for optical short pulse trains. We have successfully implemented two, four, and eight times multiplications with the maximum repetition rate of 416.7 ㎓. The obtained pulse delays are well matched with the simulated ones.