1 |
A.P. Vinod et al., "An Improved Common Subexpression Elimination Method for Reducing Logic Operators in FIR Filter Implementations without Increasing Logic Depth," INTEGRATION,VLSI J., vol. 43, 2010, pp. 124-135.
DOI
ScienceOn
|
2 |
M. Mehendale, S.D. Sherlekar, and G. Venkatesh, "Synthesis of Multiplier-less FIR Filters with Minimum Number of Additions," Proc. IEEE/ACM Int. Conf. Comput.-Aid. Design, 1995, pp. 668- 671.
|
3 |
A.P. Vinod et al., "FIR Filter Implementation by Efficient Sharing of Horizontal and Vertical Common Subexpressions," Electron. Lett., vol. 39, no. 2, Jan. 2003, pp. 251-253.
DOI
ScienceOn
|
4 |
R.I. Hartley, "Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers," IEEE Trans. Circuits Syst. II, vol. 43, no. 10, Oct. 1996, pp. 677-688.
DOI
ScienceOn
|
5 |
R. Pasko et al., "A New Algorithm for Elimination of Common Subexpressions," IEEE Trans. Comput.-Aid. Design Integ. Circuits Syst., vol. 18, no. 1, Jan. 1999, pp. 58-68.
DOI
ScienceOn
|
6 |
M.M. Peiro, E.I. Boemo, and L. Wanhammar, "Design of High- Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm," IEEE Trans. Circuits Syst. II, vol. 49, no. 3, Mar. 2002, pp. 196-203.
DOI
ScienceOn
|
7 |
Y. Takahashi and Michio Yokoyama, "A Comparison of Multiplierless Multiple Constant Multiplication Using Common Subexpression Elimination Method," 51st Midwest Symp. Circuits Syst., 2008, pp. 298-301.
|
8 |
Y. Takahashi and M. Yokoyama, "New Cost-Effective VLSI Implementation of Multiplierless FIR Filter using Common Subexpression Elimination," Proc. Int. Symp. Circuits Syst., vol. 2, May 2005, pp. 1445-1448.
|
9 |
H. Choo, K. Muhammad, and K. Roy, "Complexity Reduction of Digital Filters Using Shift Inclusive Differential Coefficients," IEEE Trans. Signal Process, vol. 52, no. 6, June 2004, pp. 1760- 1772.
DOI
ScienceOn
|
10 |
Y.B. Jang and S.J. Yang, "Low-Power CSD Linear Phase FIR Filter Structure Using Vertical Common Sub-expression," Electron. Lett., vol. 38, no. 15, July, 2002, pp. 777-779.
DOI
ScienceOn
|
11 |
F. Xu, C.H. Chang, and C.C. Jong, "Modified Reduced Adder Graph Algorithm for Multiplierless FIR Filters," Electron. Lett., vol. 41, no. 6, Mar. 2005, pp. 302-303.
DOI
ScienceOn
|
12 |
R. Hashemian, "A New Method for Conversion of a 2's Complement to Canonic Signed Digit Number System and its Representation," 30th Asilomar Conf. Signals Syst. Comput., vol. 2, 1996, pp. 904-907.
|
13 |
K. Muhammad and K. Roy, "A Graph Theoretic Approach for Synthesizing very Low-Complexity High-Speed Digital Filters," IEEE Trans. Comput.-Aid. Design Integr. Circuits, vol. 21, no. 2, Feb. 2002, pp. 204-216.
DOI
ScienceOn
|
14 |
C.Y. Yao et al., "A Novel Common-Subexpression-Elimination Method for Synthesizing Fixed-Point FIR Filters," IEEE Trans. Circuits Syst. I, vol. 51, no. 11, Nov. 2004, pp. 2215-2221.
DOI
ScienceOn
|
15 |
F. Xu, C.H. Chang, and C.C. Jong, "Contention Resolution Algorithm for Common Subexpression Elimination in Digital Filter Design," IEEE Trans. Circuits Syst. II, vol. 52, no. 10, Oct. 2005, pp. 695-700.
|
16 |
D.R. Bull and D.H. Horrocks, "Realisation Techniques for Primitive Operator Infinite Impulse Response Digital Filters," Proc. Int. Symp. Circuits Syst., vol. 1, May 1993, pp. 607-610.
|
17 |
A.G. Dempster and M.D. Mcleod, "Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters," IEEE Trans. Circuits Syst. II, vol. 42, no. 9, Sept. 1995, pp. 569-577.
DOI
ScienceOn
|
18 |
Y. Voronenko and M. Pushcel, "Multiplierless Multiple Constant Multiplication," ACM Trans. Algorithms, vol. 3, no. 2, 2007
|
19 |
J.H. Han and I.C. Park, "FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient," IEEE Trans. Comput.- Aid. Design Integrat. Circuits Syst., vol. 27, no. 5, May 2008, pp. 958-962.
DOI
|
20 |
A.P. Vinod and E.M.K. Lai, "On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods," IEEE Trans. Comput.-Aid. Design Integ. Circuits Syst., vol. 24, no. 2, Feb. 2005, pp. 295-304.
DOI
|
21 |
Y. Wang and K. Roy, "CSDC: A New Complexity Reduction Technique for Multiplierless Implementation of Digital FIR Filters," IEEE Trans. Circuits Syst. I, vol. 52, no. 9, Sept. 2005, pp. 1845-1853.
DOI
|
22 |
A.G. Dempster, S.S. Dimirsoy, and I. Kale, "Designing Multiplier Blocks with Low Logic Depth," Proc. IEEE Int. Symp. Circuits Syst., vol. 5, May 2002, pp. 773-776.
|
23 |
H. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients," IEEE Trans. Circuits Syst., vol. 36, no. 7, July 1989, pp. 1044- 1047.
DOI
ScienceOn
|
24 |
Y.C. Lim and S.R. Parker, "Discrete Coefficient FIR Digital Filter Design Based upon LMS Criteria," IEEE Trans. Circuits Syst., vol. 30, no. 10, Oct. 1983, pp. 723-739.
DOI
|