• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.197-208
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• 1999

In this paper, we proposed a multimedia hardware architecture for video-conferencing in view of the multimedia data flow. By simulating the architecture model, we analyzed the bottleneck of multimedia data flow, varying video size, frame rate, number of participants, and video data compression rate. To confirm the simulation results, we also implemented and tested the architecture that almost includes the analyzed requirements for video- conferencing. From the analysis of I/O system, we found the considerations in designing a multimedia I/O system.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1380-1382
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• 1996

In this paper, a motion estimation module is made with ADSP-21020 based on MPEG-2 which is an international standard for moving picture compression. And, the block matching algorithm used as motion estimation method is easy for an hardware implementation. The ADSP-21020 of Analog Device is used for a main control processor. We used three block matching method (exhaustive search method, 2D-logarithmic search method, three step search method) for software simulation and implemented the three step search method to hardware. For the test of the estimation module, we used ping pong image sequences and mobile and calendar image sequences.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.3306-3311
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• 2011

Last Subway video surveillance system consists of a network device that is used. Through the network to transmit video data to digital conversion of analog video via a process server or a PC video to a split-screen in various forms is expressed. In recent years, multi-monitor video cameras from the same pop-up or more, such as history, structure expressed on a variety of video is required by express. The problem with these systems, video compression and transmission of many cameras, and this image data received from the server or PC to take out all the images you want to watch to occur when in order to express all of the images because of the need to decode most of the program per limit of number of channels is positioned. This limited number of channels to have a video that nothing forced, but it is likely to do so in the future performance of the hardware evolves gradually channeled images available number of channels will increase proportionately. However, as the development of hardware required for a single screen video channel will be more gradual capital. The hardware rather than relying solely on the performance of the decoded video data on the screen in order to express a more efficient utilization of shared memory for video surveillance software will provide the operating plan.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.200-208
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• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.29-33
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• 2008

This paper presents the proposal and hardware design of JPEG baseline encoder. The JPEG encoder system consists of line buffer, 2-D DCT, quantization, entropy encoding, and packer. A fully pipelined scheme for JPEG encoder is adopted to speed-up an image compression. The proposed architecture was described in VHDL and synthesized in Xilinx ISE 7.1i and simulated by modelsim 6.1i. The results showed that the performance of the designed JPEG baseline encoder is higher than that demanded by real-time applications for $1024{\times}768$ image size. The designed JPEG encoder IP can be easily integrated into various application systems, such as scanner, PC camera, color FAX, and network camera, etc.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.192-194
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• 2005

Acceptance of the international standards for video compression, such as H.261, MPEG-1 and MPEG-2, along with the developments in video codec hardware, has created an explosion of application. Among these, the long time quest for long-distance digital video transmission causes an increasing interest in transporting compressed video over networks which are nontraditional for this purpose, including asynchronous transfer mode networks, the Internet, and cellular and wireless channels. Transmission of compression video over packet network is improved for error resilience. And layered video coding techniques improves error resilience. We present a efficient method of scalable video coding for low bandwidth.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.23-25
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• 2007

The partial distortion elimination (PDE) scheme is used to decrease the sum of absolute difference (SAD) computational complexity, since the SAD calculation has been taken much potion of the video compression. In motion estimation (ME) based on PDE, it is ideal that the initial value of SAD in summing performance has large value. The traditional scan order methods have many operation time and high operational complexity because these adopted the division or multiplication. In this paper, we introduce the new scan order and search order by using only adder. We define the average value which is called to rough average value (RAVR). Which is to reduce the computational complexity and increase the operational speed and then we can obtain the improvement of SAD performance. And also this RAVR is used to decide the search order sequence, since the difference RAVR between the current block and candidate block is small then this candidate block has high probability to suitable candidate. Thus, our proposed algorithm combines above two main concepts and suffers the improving SAD performance and the easy hardware implementation methods.