Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Pipelined Implementation of JPEG Baseline Encoder IP

  • Kim, Kyung-Hyun (Department of Information and Communications, Hanshin University) ;
  • Sonh, Seung-Il (Department of Information and Communications, Hanshin University)
  • Published : 2008.03.31
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Abstract

This paper presents the proposal and hardware design of JPEG baseline encoder. The JPEG encoder system consists of line buffer, 2-D DCT, quantization, entropy encoding, and packer. A fully pipelined scheme for JPEG encoder is adopted to speed-up an image compression. The proposed architecture was described in VHDL and synthesized in Xilinx ISE 7.1i and simulated by modelsim 6.1i. The results showed that the performance of the designed JPEG baseline encoder is higher than that demanded by real-time applications for $1024{\times}768$ image size. The designed JPEG encoder IP can be easily integrated into various application systems, such as scanner, PC camera, color FAX, and network camera, etc.

Keywords

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