• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.45-45
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• 2000

This paper proposes a remote control system that combines computer network and an autonomous mobile robot. We control remotely an autonomous mobile robot with vision via the internet to guide it under unknown environments in the real time. The main feature of this system is that local operators need a World Wide Web browser and a computer connected to the internet communication network and so they can command the robot in a remote location through our Home Page. The hardware architecture of this system consists of an autonomous mobile robot, workstation, and local computers. The software architecture of this system includes the server part for communication between user and robot and the client part for the user interface and a robot control system. The server and client parts are developed using Java language which is suitable to internet application and supports multi-platform. Furthermore, this system offers an image compression method using motion JPEG concept which reduces large time delay that occurs in network during image transmission.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.63-67
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• 1997

The ISO(International Standard Organization) has standardized MPEG-2 audio. The MPEG-2 audio compression algorithm is based upon subband analysis and exploits the human auditory characteristics to achieve a low bit rate with minimum perceptual loss of audio signal quality. This thesis presents an enhanced MPEG-2 audio encoder using multiple TMS320C30 general purpose DSP's. The developed system is made up of five slave boards and one master board. Each slave board performs susband analysis psychoacoustic parameter calculation for one channel, and the master board manages bit allocation, quantization, and bit-stream formatting for all channels. Parallel processing and pipelining techniques are used in hardware structure and fast algorithms are applied in each subroutine to implement a real-time process. The implemented system supports multichannel up to 5.1 and various bitrates.

• Proceedings of the IEEK Conference
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• summer
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• pp.114-117
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• 2004

This paper proposes a novel algorithm for hybrid lossless audio coding, which employs integer discrete cosine transform. The proposed algorithm divides the input signal into frames of a proper length, decorrelates the framed data using the integer DCT and finally entropy-codes the frame data. In particular, the adaptive Golomb-Rice coding method used for the entropy coding selects an optimal option which gives the best compression efficiency. Since the proposed algorithm uses integer operations, it significantly improves the computation speed in comparison with an algorithm using real or floating-point operations. When the coding algorithm is implemented in hardware, the system complexity as well as the power consumption is remarkably reduced. Finally, because each frame is independently coded and is byte-aligned with respect to the frame header, it is convenient to move, search, and edit the coded data.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1823-1826
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• 2002

On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.59-68
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• 1998

This paper propose a hardware architecure of multimediasysgem for integrated processing of the multimedia data such as audio and video, and describes on the design and implementation of multimedia integrated processing Unit. The unit comprises most commonly needed multimedia processing function for computer-based video conference: audio-visual datacapture, playback, compression, decompression as well as interleaving/disinterleaving of compressed audio-visual data. The proposed architecture minimizes the CPU overhead that might be caused by multimedia data processing and assures the fluent data flow among system components. Also, this unit is tested and analyzed under the computer-based video conference to confirm the multimedia unit of proposed architecture using communication protocol and application software through Ethernet and FDDI (Fiber Distributed Data Interface) networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.557-564
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• 2000

This paper presents a watermarking algorithm for embedding visually recognizable pattern (Mark, Logo, Symbol, stamping or signature) into the image. first, the color image(RGB model)is transformed in YCbCr model and then the Y component is transformed into 3-level wavelet transform. Next, the values are assembled with pattern watermark. PN(pseudo noise) code at spread spectrum communication method and mutilevel watermark weights. This values are inserted into discrete wavelet domain. In our scheme, new calculating method is designed to calculate wavelet transform with integer value in considering the quantization error. and we used the color conversion with fixed-point arithmetic to be easy to make the hardware hereafter. Also, we made the new solution using mutilevel threshold to robust to common signal distortions and malicious attack, and to enhance quality of image in considering the human visual system. the experimental results showed that the proposed watermarking algorithm was superior to other similar water marking algorithm. We showed what it was robust to common signal processing and geometric transform such as brightness. contrast, filtering. scaling. JPEG lossy compression and geometric deformation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.608-616
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• 1996

In this paper, we propose a multimedia hardware architecture for desktop video-conferencing in view of the multimedia data flow and analyze system operation using queueing model. We analyze the bottleneck of multimedia data flow for video- conferencing by simulation, varying the video size, frame rate, the number of participants, and video data compression rate, And we also implement and test the archiecture, that almost includes the analyzed requirements for video-conferencing, to confirm the simulation results. This paper describes the considerations in designing a multimedia I/O system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.315-323
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• 1987

Generally, general-purpose image processing system is so expensive that not so many users easily can access the system. In this paper attemps have been made to design and describe a general and economical image processing system for real-time aplications such as image data compression, pattern recognition and target tracking. The system comprises an operator console, image data acquisition/display sistem and IBM PC/XT. The system also utilizes a high speed Fairchild 16-bit microprocessor with ALU speed of 375 nsec for system control, algrithm execution and user computation. The system also can digitize /display a 256x 256x 8 bit image in real time and store two frames of images. All image pixels are directly accessible by the microprocessor for fast and efficient computation. Some experimental and illustrative results such as target tracking are presented to show the efficient performance of the system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.344-354
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.