• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.425-430
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• 2003

A CMOS Voltage-Controlled Oscillator(VCO) for application at temperature stable system is designed. The VCO consists of bandgap voltage reference circuit, comparator, and voltage-to-current converter and the VCO has a temperature stable characteristics. The difference between simulated and calculated values is less than about 5% in output characteristics when the input voltage range is from 1V to 3.25V. The CMOS VCO has error less than about $\pm$0.85% in the temperature range from $-25^{\circ}C$ to $75^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.61-66
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• 1984

In this paper a custom design of CMOS PLA using procedual language, CHISEL is presented. Library of cells of PLA pieces are formed. A typical PLA is used as a control logic for the protector circuit. NCR's design rules are applied to program CMOS PLA using CHISEL which is a VILI layout language made by extending C language.

• Imaging Science in Dentistry
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• v.34 no.1
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• pp.1-5
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• 2004

Purpose: To evaluate the diagnostic accuracy of occlusal and proximal caries detection using CCD, CMOS, PSP and film system. Materials and Methods : 32 occlusal and 30 proximal tooth surfaces were radiographed under standardized conditions using 3 digital systems; CCD (CDX-2000HQ, Biomedysis Co., Seoul, Korea), CMOS (Schick, Schick Inc., Long Island, USA), PSP (Digora/sup (R)/FMX, Orion Co./Soredex, Helsinki, Finland) and I film system (Kodak Insight, Eastman Kodak, Rochester, USA). 5 observers examined the radiographs for occlusal and proximal caries using a 5-point confidence scale. The presence of caries was validated histologically and radiographically. Diagnostic accuracy was evaluated using ROC curve areas (Az). Results: Analysis using ROC curves revealed the area under each curve which indicated a diagnostic accuracy. For occlusal caries, Kodak Insight film had an Az of 0.765, CCD one of 0.730, CMOS one of 0.742 and PSP one of 0.735. For proximal caries, Kodak Insight film had an Az of 0.833, CCD one of 0.832, CMOS one of 0.828 and PSP one of 0.868. No statistically significant difference was noted between any of the imaging modalities. Conclusion: CCD, CMOS, PSP and film performed equally well in the detection of occlusal and proximal dental caries. CCD, CMOS and PSP-based digital images provided a level of diagnostic performance comparable to Kodak Insight film.

• Journal of Electrical Engineering and Technology
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• v.8 no.5
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.77-84
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• 1998

The continuous time signal system by development of CMOS technology have been receiving consideration attention. In this paper, Low pass filter using CMOS floating resistor have been designed with cut off frequency for speech signal processing. Especially a new floating resistor consisting entirely of CMOS devices in saturation has been developed. Linearity within $\pm$0.04% is achieved through nonlineartiy via current mirrors over an applied range of $\pm$1V. The frequency response exceeds 10MHz, and the resistors are expected to be useful in implementing integrated circuit active RC filters. The low pass filter designed using this method has simpler structure than switched capacitor filter. So reduce the chip area. The characteristics of the designed low pass filter using this method are simulated by pspice program.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.131-139
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• 1989

This paper proposes Domino CMOS NOR-NOR Array Logic design method which has the same as characteristic of CMOS and Domino CMOS in Array Logic like PLA, good operation feature, high desity, easy test generation. This testable design method can detect all of faults in the circuit using simple additional circuit and solve the parasitic capacitance problem by improving the pull-down characteristics. A Test generation algorithm and test procedure using concept of PLA product term and personality matrix are proposed, and it was implemented in PASCAL language. This design method is verified by SPICE and P-SPICE simulation.

• ETRI Journal
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• v.21 no.4
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• pp.1-8
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• 1999

Thick metal 0.8${\mu}m$ CMOS technology on high resistivity substrate(RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15mA that is an excellent noise performance compared with the offchip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integrating of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatibel process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.55-63
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• 1999

A new CMOS If Package design methodology is presented, analyzing the electrical characteristics of a package and its effects on the CMOS digital circuits. An analytical investigation of the package noise effects due to the simultaneous switching of the gates within a chip, i.e., simultaneous switching noise (SSN) is performed. Then not only are novel design formula to meet electrical constraints of the Package derived, but also package design methodology based on the formula is proposed. Further, in order to demonstrate the Proposed design methodology, the design results are compared with HSPICE (a general purpose circuit simulator) simulation for $0.3\mu\textrm{m}$-based CMOS circuits. According to the proposed design procedures, it is shown that the results have excellent agreements with those of HSPICE simulation.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.