• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12A
• /
• pp.2000-2011
• /
• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• Journal of Satellite, Information and Communications
• /
• v.4 no.2
• /
• pp.39-45
• /
• 2009

This paper proposes the specific code synchronization technique for DS-SS(Direct Sequence-Spread Spectrum transmission in the DVB-RCS +M standard. DS-SS is better than multi-carrier transmission method under nonlinear channel but imposes a long acquisition time. To improve the synchronization aspect, the robust correlation structure is introduced for acquisition and the nonlinear delay lock loop is done for tracking. MAT(Mean Acquisition Time) performances is shown to validate its superiority. In addition, code tracking and jitter performances are done when code tracking algorithm based on 2 oversamples which is not influenced by sampling clock timing offset and carrier freq. offset is used.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.1
• /
• pp.110-116
• /
• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.6A
• /
• pp.871-880
• /
• 1999

In this paper, a pseudo-noise(PN) tracking and demodulation circuits are analyzed and designed for a direct-sequence/spread-spectrum multiple access system under a mobile fading channel. We consider noncoherent delay locked loop(DLL) as a PN code tracking loop which has 1/8 PN chip resolution. The tracking performance of DLL is evaluated in terms of locking time from a loose state and tracking jitter. The received signal is demodulated to original data by despreading with PN code locked by DLL. Also the designed circuit supports sound service of 32Kbps and in-band signal with 4.096MHz chip clock. The circuits are implemented and verified with FPGA, which is shown completely data recovery under AWGN 7dB and will be available for IMT-2000.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.10
• /
• pp.11-18
• /
• 1998

A binary line code, called MB46d, is designed by use of the BUDA(Binary Unit DSV and ASV) cell concept to retain the property of being runlength limited, DC tree, and with a power spectral null at the Nyquist frequency. This new code is a stateless line code with a simple encoding and a decoding rule and enables efficient error monitoring. The power spectrum and the eye pattern of the new line code are simulated for a minimum-bandwidth digital transmission system where the sinc function is used as a basic pulse. The obtained power null at the Nyquist frequency is wide enough to enable easy band-limiting as well as secure insertion of a clock pilot where necessary. The eye is also substantially wide to tolerate a fair amount of timing jitter in the receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.46-51
• /
• 2002

A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.1 no.2
• /
• pp.145-158
• /
• 1997

Method for synchronizing multimedia data is needed to support continuous transmission of multimedia data through a network in a bounded time and it also required for supporting continuous presentation of multimedia data with the required norminal playout rate in distributed network environments. This paper describes a new synchronization method for supporting delay-sensitive multimedia Presentation without degration of Quality of services of multimedia application. It mainly aims to support both intermedia and intermedia synchronization by absorbing network variations which may cause skew or jitter. In order to remove asynchonization problems, we make use of logical time system, dynamic buffer control method, and adjusting synchronization intervals based on the quality of services of a multimedia. It might be more suitable for working on distribute[1 multimedia systems where the network delay variation is changed from time to time and no global clock is supported. And it also can effectively reduce the amount of buffer requirements needed for transfering multimedia data between source and destination system by adjusting synchronization intervals with acceptable packet delay limits and packet loss rates.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.5
• /
• pp.1103-1108
• /
• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.21-31
• /
• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.