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Low Power Clock Generator Based on An Area-Reduced Interleaved Synchronous Mirror Delay Scheme  

Seong, Gi-Hyeok (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
Park, Hyeong-Jun (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
Yang, Byeong-Do (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
Kim, Lee-Seop (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.8, 2002 , pp. 46-51 More about this Journal
Abstract
A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.
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1 T. Saeki et al., 'A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,' IEEE J. Solid-State Circuits, Vol. 31, pp. 1656-1665, Nov. 1996   DOI   ScienceOn
2 T. Saeki et al., 'A 10ps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock generator Based on an Interleaved Synchronous Mirror Delay Scheme,' in Proc. Symp. VLSI Circuits, pp. 109-110, June 1997
3 J. Yuan and C. Svensson, 'High-Speed CMOS Circuit Technique,' IEEE J. Solid-State Circuits, Vol. 24, pp. 62-70, Feb. 1989   DOI   ScienceOn
4 T. Saeki et al., 'A Direct-Skew-Detect Synchronous Mirror Delay for Application Specific Integrated Circuits,' IEEE J. Solid-State Circuits, Vol. 34, pp. 372-379, Mar. 1999   DOI   ScienceOn