• Title/Summary/Keyword: clock jitter

Search Result 139, Processing Time 0.023 seconds

3.125Gbps Reference-less Clock/Data Recovery using 4X Oversampling (레퍼런스 클록이 없는 3.125Gbps 4X 오버샘플링 클록/데이터 복원 회로)

  • Lee, Sung-Sop;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.10 s.352
    • /
    • pp.28-33
    • /
    • 2006
  • An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

  • Song, Jae-Ho;Yoo, Tae-Whan;Ko, Jeong-Hoon;Park, Chang-Soo;Kim, Jae-Keun
    • ETRI Journal
    • /
    • v.21 no.3
    • /
    • pp.1-5
    • /
    • 1999
  • A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

  • PDF

A Method of Selecting Filter Coefficient for Robust Data to Clock Equalizer in Optical Disc Drive (광 디스크 드라이브의 강인한 데이터-클럭 등화기 필터계수 선정)

  • Yeom, Dong-Hae;Kim, Jin-Kyu;Joo, Young-Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.59 no.4
    • /
    • pp.793-796
    • /
    • 2010
  • The equalizer compensates a signal distorted by transmission lines and amplifying stages, so the signal can have uniform characteristics over all frequency range. The equalizer in ODD(Optical Disc Drive) improves the stability of the extracted clock from a received signal and the readability of an inserted disc by suppressing noise and ISI(Inter-Symbol Inference). The length of marks-spaces and track pitch on discs becomes shorter as the recording density of an optical media is higher, which causes noise and ISI. And, the sensitivity about the fluctuation of physical systems is higher as the optical devices become more complicate. This paper proposes a method to select the coefficient of built-in equalizer of ODD in order to maintain the quality of signals against noise and ISI caused by system fluctuation.

A Design Study of Phase Detectors for the 2.5 Gb/s Clock and Data Recovery Circuit (2-5 Gb/s 클럭-데이터 복원기를 위한 위상 비교기 설계 연구)

  • 이영미;우동식;유상대;김강욱
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
    • /
    • 2002.11a
    • /
    • pp.394-397
    • /
    • 2002
  • A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

  • PDF

A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

  • Park, Geontae;Kim, Hyungtak;Kim, Jongsun
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.13 no.5
    • /
    • pp.459-464
    • /
    • 2013
  • A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

Multiphase PLL using a Vernier Delay VCO (버니어 지연 VCO를 이용한 다중위상발생 PLL)

  • Sung, Jae-Gyu;Kango, Jin-Ku
    • Journal of IKEEE
    • /
    • v.10 no.1 s.18
    • /
    • pp.16-21
    • /
    • 2006
  • This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

  • PDF

Design and Fabrication of 10Gb/s FPLL Clock and Data Regeneration Circuit (10Gb/s FPLL 방식 클럭/데이터 재생회로 설계 및 제작)

  • Song, Jae-Ho;Yoo, Tae-Hwan;Park, Chang-Soo
    • Journal of the Korean Institute of Telematics and Electronics S
    • /
    • v.35S no.12
    • /
    • pp.1-7
    • /
    • 1998
  • in this work, we designed and characterized a 10Gb/s clock and regeneration circuit. The circuit was realized by integrating high-speed ICs and microwave circuits on alumina substrates. The quadri-correlation method was used for frequency and phase-locked loop. The frequency locking range was 150MHz and the rms jitter generated by the circuit was measured to be less than 1.0ps. The clock and data regeneration circuit was successfully applied to 10Gb/s optical receiver.

  • PDF

Design of a 2.5 Gb/s Clock and Data Recovery Circuit (2.5 Gb/s 클럭 및 데이터 복원 회로의 설계)

  • Lee, Young-Mi;Woo, Dong-Sik;Lee, Ju-Sang;Kim, Kang-Wook;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
    • /
    • 2002.11c
    • /
    • pp.593-596
    • /
    • 2002
  • A design of clock and data recovery (CDR) circuit for the SONET OC-48 using a standard 0.18 ${\mu}m$ CMOS process has been performed. The phase detector and the charge pump must be able to operate at the 2.5 Gb/s input data speed and also accurately compare phase errors to reduce clock jitter. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output. A general ring oscillator topology is presented and simulated. It provides five-phase outputs and 220 MHz to 3.12 GHz tuning range.

  • PDF

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

  • Lee, Kwang-Hun;Jang, Young-Chan
    • Journal of information and communication convergence engineering
    • /
    • v.10 no.2
    • /
    • pp.187-193
    • /
    • 2012
  • A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

Dual-Mode Reference-less Clock Data Recovery Algorithm (이중 모드의 기준 클록을 사용하지 않는 클록 데이터 복원 회로 알고리즘)

  • Kwon, Ki-Won;Jin, Ja-Hoon;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.53 no.5
    • /
    • pp.77-86
    • /
    • 2016
  • This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.