• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.23 no.8
• /
• pp.80-85
• /
• 2009

In this paper, we propose a full digital capacitive sensing touch key reducing the effects due to the variations of resistance and clock frequency. The proposed circuit consists of two capacitive loads to measure and a resistor between the capacitive loads. The method measures the delays of the resistor and two capacitive loads, respectively. The ratio of the two delays is represented as the ratio of the two capacitive loads and is irrelative to the resistance and the clock frequency if quantization error is disregarded. Experimental results show the proposed scheme efficiently reduces the effects due to the variations of clock frequency and resistance. Further more the method has 1.04[pF] resolution and can be used as a touch key.

• Journal of Power Electronics
• /
• v.11 no.3
• /
• pp.271-278
• /
• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Korean Journal of Schizophrenia Research
• /
• v.23 no.1
• /
• pp.15-28
• /
• 2020

Objectives: This study investigated the relationship between clock-drawing test (CDT) performance and neuropsychological functions in patients with chronic schizophrenia. Methods: Thirty-one patients with schizophrenia and 30 healthy controls participated in this study. The CDT was administered in three conditions and analyzed using both quantitative and qualitative scoring systems. Comprehensive neuropsychological tests were administered. Results: The results of the quantitative analysis showed that the schizophrenia group performed significantly worse in all three conditions of the CDT compared with the control group. However, no significant differences were observed between the two groups, when the IQ and educational level were controlled. The qualitative analysis showed that the schizophrenia group exhibited significantly more errors in "graphic difficulty" compared with the control group. In addition, CDT quantitative scores were significantly correlated with visuospatial function, memory, attention and executive functions in patients with schizophrenia. Conversely, each qualitative error type was correlated with specific cognitive domains. Furthermore, "graphic difficulty" and "spatial/planning deficit" were identified as predictors of depression symptoms in patients with schizophrenia. Conclusion: The present study demonstrated that the CDT is useful for assessing cognitive dysfunctions in patients with schizophrenia, while qualitative analyses provide more specific information about cognitive deficits compared with quantitative analyses.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.4
• /
• pp.161-166
• /
• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2000.11a
• /
• pp.179-183
• /
• 2000

This paper is concerned with achieving the high motion accuracy of linear motion bearing guide according to estimate accuracy average effect of bearing. Accuracy average effect can be obtained b analysis the relationship between motion error of the table and spatial frequency of the rail form error. And influences of ball diameter, ball number, and clock length on block motion error and block number on the table motion error are analyzed theoretically. In addition to, a simple experiment is performed in order to verify theoretical result.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.10
• /
• pp.1483-1488
• /
• 2012

This paper analyzed the precision and accuracy of the altitude-aided GNSS using the altitude information from digital map. The precision of altitude-aided GNSS is analysed using the theoretically derived DOP. It is confirmed that the precision of altitude-aided GNSS is superior to the general 3D positioning method. It is also shown that the DOP of altitude-aided GNSS is independent of altitude bias error while the accuracy was influenced by the altitude bias error. Furthermore, it is shown that, since the altitude bias error influenced differently to each pseudorange measurement, the effect of the altitude bias error is more serious than clock bias error which does not influence position error at all. The results are evaluated by the simulation using the commercial RF simulator and GPS receiver. It confirmed that altitude-aided GNSS could improve not only precision but also accuracy if the altitude bias error are small. These results are expected to be easily applied for the performance improvement to the land and maritime applications.

• ETRI Journal
• /
• v.21 no.3
• /
• pp.1-5
• /
• 1999

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.48-55
• /
• 2017

This paper proposes a new link structure that transmits power, clock, and data through a single optical fiber for a future automotive network. A pulse-position modulation (PPM) technique is adopted to guarantee a DC-balanced signal for robust power transmission regardless of transmitted data pattern. Further, circuit implementations and theoretical analyses for the proposed PPM transceiver are described in this paper. A prototype transceiver fabricated in 65-nm CMOS technology, is used to verify the PPM signaling part of the proposed system. The prototype achieves a $10^{-13}$ bit-error rate and 0.188-UI high frequency jitter tolerance while consuming 14 mW at 800 Mb/s.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.152-156
• /
• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.522-523
• /
• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.