• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.9
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• pp.757-765
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• 2017

GNSS (Global Navigation Satellite System) Position Accuracy depends on pseudo-range measurement and DOP (Dilution Of Precision) which indicates about navigation satellite geometry. Pseudo-Range has many error sources such as satellite clock, orbit, ionosphere, troposphere, multipath and so on. For the improvement of the accuracy, user can use corrected pseudo-range in DGPS (Differential Global Positioning System), which is one of the relative positioning methods. But, stationary station is needed in relative positioning. In case of DOP, Signal reception environment is important. If receiver sets in the center of city, it could be interrupted reception by buildings. This environment leads to decrease the number of visible satellites and to increase DOP. This paper proposes the concept of GNSS positioning with virtual satellites which have usable VRM (Virtual Range Measurement). Via virtual satellites and VRM, users could get an accurate position. Especially referred virtual satellites constellation has an effect on vertical error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• Communications of Mathematical Education
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• v.38 no.2
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• pp.145-165
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• 2024

The purpose of this study is to analyze the types of errors made by Korean language learners in the use of dual numerals and provides basic data for developing an effective teaching numeration using dual numerals. To this end, a case study was conducted to analyze the types of errors that appear in numeration using dual numerals targeting Korean language learners with diverse linguistic and cultural backgrounds and different academic achievements in Korean and mathematics. Error types that categorized errors made by Korean language learners were used as an analysis framework. The conclusions obtained from the research results are as follows. First, it is necessary to provide students with opportunities to use them frequently so that they can become familiar with the use of native language numerals, which often causes errors. Second, when teaching Korean language learners with low-level Korean language academic achievement how to use Chinese numerals, it is necessary to pay attention to the multiplicative numeral system of Chinese numerals. Third, it is necessary to teach children to accurately read foreign word classifiers used with Chinese numerals accurately in Korean and distinguish between the classifiers 'o'clock' and 'hours'. There is a need to provide guidance so that native language/Chinese numerals can be used appropriately in succession along with Chinese classifiers. The results of this study may contribute to the development of an effective teaching numeration using dual numerals for Korean language learners with diverse linguistic and cultural backgrounds.

• Korean Journal of Agricultural and Forest Meteorology
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• v.11 no.2
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• pp.61-71
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• 2009

Most deciduous trees in temperate zone are dormant during the winter to overcome cold and dry environment. Dormancy of deciduous fruit trees is usually separated into a period of rest by physiological conditions and a period of quiescence by unfavorable environmental conditions. Inconsistent and fewer budburst in pear orchards has been reported recently in South Korea and Japan and the insufficient chilling due to warmer winters is suspected to play a role. An accurate prediction of the flowering time under the climate change scenarios may be critical to the planning of adaptation strategy for the pear industry in the future. However, existing methods for the prediction of budburst depend on the spring temperature, neglecting potential effects of warmer winters on the rest release and subsequent budburst. We adapted a dormancy clock model which uses daily temperature data to calculate the thermal time for simulating winter phenology of deciduous trees and tested the feasibility of this model in predicting budburst and flowering of Niitaka pear, one of the favorite cultivars in Korea. In order to derive the model parameter values suitable for Niitaka, the mean time for the rest release was estimated by observing budburst of field collected twigs in a controlled environment. The thermal time (in chill-days) was calculated and accumulated by a predefined temperature range from fall harvest until the chilling requirement (maximum accumulated chill-days in a negative number) is met. The chilling requirement is then offset by anti-chill days (in positive numbers) until the accumulated chill-days become null, which is assumed to be the budburst date. Calculations were repeated with arbitrary threshold temperatures from $4^{\circ}C$ to $10^{\circ}C$ (at an interval of 0.1), and a set of threshold temperature and chilling requirement was selected when the estimated budburst date coincides with the field observation. A heating requirement (in accumulation of anti-chill days since budburst) for flowering was also determined from an experiment based on historical observations. The dormancy clock model optimized with the selected parameter values was used to predict flowering of Niitaka pear grown in Suwon for the recent 9 years. The predicted dates for full bloom were within the range of the observed dates with 1.9 days of root mean square error.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.6
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• pp.18-26
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• 2011

Debates concerning the competitive edge of leading 3DTV technology of the shutter glasses (SG) 3D and the film-type patterned retarder (FPR) are flaring up. Although SG technology enables Full-HD 3D vision, it requires complex systems including the sync transmitter (emitter), the sync processor chip, and the LCD lens in the active shutter glasses. In addition, the transferred sync-signal is easily affected by the external noise and a 3DTV viewer may feel flicker-effect caused by cross-talk of the left and right image. The operating current of the sync processor in the 3DTV active shutter glasses is gradually increasing to compensate the sync reconstruction error. The proposed chip is a low-power hardware sync processor based discrete-event SoC(system on a chip) designed specifically for the 3DTV active shutter glasses. This processor implements the newly designed power-saving techniques targeted for low-power operation in a noisy environment between 3DTV and the active shutter glasses. This design includes a hardware pre-processor based on a universal edge tracer and provides a perfect sync reconstruction based on a floating-point timer to advance the prior commercial 3DTV shutter glasses in terms of their power consumption. These two techniques enable an accurate sync reconstruction in the slow clock frequency of the synchronization timer and reduce the power consumption to less than about a maximum of 20% compared with other major commercial processors. This article describes the system's architecture and the details of the proposed techniques, also identifying the key concepts and functions.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.2
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• pp.43-55
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• 2015

In the case of satellite navigation positioning, the shielding of satellite signals is determined by the environment of the region at which a user is located, and the navigation performance is determined accordingly. The accuracy of user position determination varies depending on the dilution of precision (DOP) which is a measuring index for the geometric characteristics of visible satellites; and if the minimum visible satellites are not secured, position determination is impossible. Currently, the GLObal NAvigation Satellite system (GLONASS) of Russia is used to supplement the navigation performance of the Global Positioning System (GPS) in regions where GPS cannot be used. In addition, the European Satellite Navigation System (Galileo) of the European Union, the Chinese Satellite Navigation System (BeiDou) of China, the Quasi-Zenith Satellite System (QZSS) of Japan, and the Indian Regional Navigation Satellite System (IRNSS) of India are aimed to achieve the full operational capability (FOC) operation of the navigation system. Thus, the number of satellites available for navigation would rapidly increase, particularly in the Asian region; and when integrated navigation is performed, the improvement of navigation performance is expected to be much larger than that in other regions. To secure a stable and prompt position solution, GPS-GLONASS integrated navigation is generally performed at present. However, as available satellite navigation systems have been diversified, finding the minimum satellite constellation combination to obtain the best navigation performance has recently become an issue. For this purpose, it is necessary to examine and predict the navigation performance that could be obtained by the addition of the third satellite navigation system in addition to GPS-GLONASS. In this study, the current status of the integrated navigation performance for various satellite constellation combinations was analyzed based on 2014, and the navigation performance in 2020 was predicted based on the FOC plan of the satellite navigation system for each country. For this prediction, the orbital elements and nominal almanac data of satellite navigation systems that can be observed in the Korean Peninsula were organized, and the minimum elevation angle expecting signal shielding was established based on Matlab and the performance was predicted in terms of DOP. In the case of integrated navigation, a time offset determination algorithm needs to be considered in order to estimate the clock error between navigation systems, and it was analyzed using two kinds of methods: a satellite navigation message based estimation method and a receiver based method where a user directly performs estimation. This simulation is expected to be used as an index for the establishment of the minimum satellite constellation for obtaining the best navigation performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2000-2011
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• 2001

In this Paper, we convert conventional low speed(1x, 6x) DVD systems designed by analog PLL(Phase Locked Loop) into digital PLL to operate at high speed systems flexibly, and present optimal DPLL model in high speed(20x) DVD systems. Especially, we focused on the design of DPLL that can overcome channel effects such as bulk delay, sampling clock frequency offset and asymmetry phenomenon in high speed DVD systems. First, the modified Early-Late timing error detector as digital timing recovery scheme is proposed. And the four-sampled compensation algorithm using zero crossing point as asymmetry compensator is designed to achieve high speed operation and strong reliability. We show that the proposed timing recovery algorithm provides enhanced performances in jitter valiance and SNR margin by 4 times and 3dB respectively. Also, the new four-sampled zero crossing asymmetry compensation algorithm provides 34% improvement of jitter performance, 50% reduction of compensation time and 2.0dB gain of SNR compared with other algorithms. Finally, the proposed systems combined with asymmetry compensator and DPLL are shown to provide improved performance of about 0.4dB, 2dB over the existing schemes by BER evaluation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.1-9
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• 2009

In this paper, a small area 12-bit 300MSPS CMOS Digital-to-Analog Converter(DAC) is proposed for display systems. The architecture of the DAC is based on a current steering 6+6 segmented type, which reduces non-linearity error and other secondary effects. In order to improve the linearity and glitch noise, an analog current cell using monitoring bias circuit is designed. For the purpose of reducing chip area and power dissipation, furthermore, a noble self-clocked switching logic is proposed. To verify the performance, it is fabricated with $0.13{\mu}m$ thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is $0.26mm^2$ ($510{\mu}m{\times}510{\mu}m$) with 100mW power consumption. The measured INL (Integrated Non Linearity) and DNL (Differential Non Linearity) are within ${\pm}3LSB$ and ${\pm}1LSB$, respectively. The measured SFDR is about 70dB, when the input frequency is 15MHz at 300MHz clock frequency.