• Journal of the Institute of Electronics Engineers of Korea TC
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• 제48권1호
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• pp.62-69
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• 2011

A novel QEGT codebook index searching algorithm for long tenn evolution (LTE) system is proposed. The proposed algorithm divides the Q precoding vectors into M groups, and selects the optimal precoding vector from the selected group at the receiver. This algorithm reduced the calculation for searching the optimal precoding vector index compared to the previous algorithms. The index searching algorithm is implemented for TI's TMS320C6713 DSP board. When the number of transmit antenna is 4, the number of clock cycles is reduced to 25%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권2호
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• pp.83-88
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• 2005

We propose the design method for the VLSI architecture of FNNPDS combined PDS(partial distance search) and FNNS(fast nearest neighbor search), which are used to fast encoding in vector quantization, and obtain the results that FNNPDS(fast nearest neighbor partial distance search) is faster method than the conventional methods by simulation. In simulations, we investigate timing diagrams described searching time of the nearest codevector for an input vector, and compare the average clock cycles per input vector for Lena and Peppers images. According to the result of simulations, the number of the clock cycle of FNNPDS was reduced to $79.2\%\~11.7\%$ as compared with the number using the conventional techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제38권12호
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제13권2호
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• pp.59-65
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• 2013

Microprocessors of 8 to 16 bits have become the first step of today's computer development with excellent capability and a lot of those are still used in the educational spots. In this study, execution times of Intel series microprocessors(${\mu}ps$) available to microprocessor systems of 8 to 32 bits are obtained and compared by I/O programs. The compared result showed that execution time related to the instruction cycles of 8 bit 8051 was longer than that of 8 bit 8051 and of 16 bit 8086 by a lot of number of clocks in cases of clock frequencies at 4 MHz and at 12 MHz. In cases of really many using ${\mu}p$ clock frequencies, it showed that execution times of instructions have become faster by the order of 8085, 8086, 8051 and 80386. It can be helped to interface with ${\mu}ps$ for real time control through comparing with execution times of I/O programs by mainly many usable Intel series ${\mu}ps$ in our nation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권11호
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제10권3호
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• pp.486-495
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• 2006

In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

• Sleep Medicine and Psychophysiology
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• 제3권2호
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• pp.18-31
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• 1996

Jet-lag can be defined as the cumulative physiological and psychological effects of rapid air travel across multiple time zones. Many reports have suggested that age-related changes in sleep reflect fundamental changes in the circadian system and in significant declines in slow wave sleep. Jet lag is a dramatic situation in which the changes of the phase of circadian process and homeostatic process of sleep occur. Thus the authors evaluatead the changes of sleep-wake cycle from jet lag by age. Thirty-eight healthy travellers were studied for 3 days before and 7 days after jet-flights across seven to ten time zone. They were aged 19-70, They trareled eastbound, Seoul to North America (USA, Canada). Sleep onset time, wake-up time, sleep latency, awakening frequency on night sleep, awakening duration on night sleep, sleepiness at wake-up and nap length were evaluated. Our results suggest that by the 7 to 10 time zone shift, the old age group was significantly influenced in sleep-wake cycles. The date on which subjective physical condition was recovered was $6.23{\pm}83$ day after arrivals for old age group, while for young and middle age group, $4.46{\pm}1.50$ day and $4.83{\pm}1.52$ day, respectively. In old age group, sleep onset time was later than baselines and could not recover untill 7th day. But in other groups, the recovery was within 5th day. Nap dura fion was longer in old age group through jet lag than younger age group. In other parameters, there was no definite difference among three age groups. Our results suggested that the old age was significantly influenced by the disharmony between internal body clock and sleep-wake cycle needed at the travel site. Thus we proved that recovery ability from jet lag was age-dependent as well as travelling direction-dependent. To demonstrate more definite evidence, EEG monitoring and staging of sleep were funthun encouraged.

• Journal of Platform Technology
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• 제12권2호
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• pp.34-44
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• 2024

This paper proposes a dynamic clock supply control algorithm and a system load power stabilization algorithm that minimizes the power consumption of the sensing system, which accounts for the largest percentage of power consumption in mobile devices, to extend the usage time of the rechargeable battery mounted on the mobile device. The dynamic clock supply control algorithm can reduce the power consumed by the sensing system by configuring a circuit to cut off the power of the sensing system and by recognizing the state of low sensor change and adjusting the measurement cycle. The system load power stabilization algorithm is an algorithm that controls the power of the surrounding module according to the power consumption state, and when it requires a lot of power, it controls the clock supply to stabilize the operation. The experimental results confirmed that applying only the dynamic clock supply control algorithm reduces the power consumed by the sensing system by 17%, and applying only the system load power stabilization algorithm reduces power consumption by 9.3%, enabling it to operate stably in situations that require a lot of power such as image processing. When both algorithms were applied, the power consumption of the battery was reduced by 67% compared to before applying the algorithm. Through this, the reliability of the proposed method was confirmed.