• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.6
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• pp.21-30
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• 1975

A method by which one can optimize the complex responses of electronic circuits has been suggested. represented in the complex forms, the optimization methods presented so far have dealt with real magnitude and phase responses of circuits. Design examples are shown on the optimal designs of an amplifier, filter, operational circuits transmission lines. and a wave-shaping circuit.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.384-387
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• 1999

In this paper, we have proposed a testing methodology for Speed-Independent asynchronous control circuits using the self-checking property where the circuit detects certain classes of faults during normal operation. To exploit self-checking properties of Speed-Independent circuits, the Proposed methodology generates tests from the specification of the target circuit which describes the behavior of the circuit. The generated tests are applied to a fault-free and a faulty circuit, and target faults can be detected by the comparison of the outputs of the both circuits. For the purpose of efficient comparison, reachability information of the both circuits in the form of BDD's is used and operations are conducted by BDD manipulations. The identification for undetectable faults in testing is also used to increase efficiency of the proposed methodology. The proposed identification uses only topological information of the target circuit and reachability information of the good circuit which was generated in the course of preprocess. Experimental results show that high fault coverage is obtained for synthesized Speed-Independent circuits and the use of the identification process decreases the number of tests and execution time.

• Journal of electromagnetic engineering and science
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• v.13 no.4
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• pp.233-239
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• 2013

This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.56-59
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• 2001

An effective method of detecting inter-turn short circuits on round rotor windings is described. Shorted-turns can have significant effects on a generator and its performance. A method of detecting inter-turn short circuits on rotor windings is described. The approach used is to measure the rate of change of the air-gap flux density wave when the rotor is at operating speed and excitation is applied to the field winding. The inter-turn short circuits sensor for synchronous generator's field winding has been developed. The sensor, installed in the generator air-gap, senses the slot leakage flux of field winding and produces a voltage waveform proportional to the rate of change of the flux. For identification of reliability for sensor, a inter-turn short circuits test was performed at the West-Inchon combined cycle power plant on gas turbine generator and steam turbine generator. This sensor will be used as a detecting of shorted-turn for field winding of synchronous generator. The purpose of this paper is to describe the design and operation of a sensitive inter-turn short circuits detector. In this paper, development of inter-turn short circuits sensor for field winding of synchronous generator and application in a field.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.3
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• pp.138-144
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• 2017

In this paper, we propose a high frequency boosting circuits compensating for age-related hearing loss. The frequency response of this hearing loss is quite similar to that of a low-pass filter of which the critical frequency get lower with age. Therefore the voltage gain of this compensation circuits increase proportionally to the frequency of signals when the frequency is higher than the critical frequency and the voltage is constant irrespective of the frequency of signals when the frequency is lower than the critical frequency. The proposed circuits consist of a differential circuit and a unity gain amplifier. Because the critical frequency of the proposed circuits is controlled simply in the shape of a volume control lever, the aged people can adjust the high frequency boosting level easily according to one's hearing loss level. The critical frequency is continuously controllable in the whole audible frequency band and the gain of this high frequency boosting circuits is above 80dB at 10kHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.2
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• pp.218-230
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• 1993

A power line modem(PLM) which transfers data safely through power lines in houses or small offices is considered. When a power line is used for communications, transmitted signals could be affected by the channel characteristics such as frequency-selective fading, interference, and time-varying attenuation. In order to overcome these impairments, a direct sequence(DS) technique which is well known as an effective instrument against a variety of interferences and hostile channel properties is employed. Using a DS technique, however, requires more circuits such as PN code generator circuits, code modification circuits, and complicated synchronization circuits, and it also results in substantial acquisition delay. In this paper, some of these circuits are implemented via software programmed in the system controller, and the complicated synchronization circuits are replaced by simple circuits utilizing a 60 Hz power signal for synchronization. The synchronization ciruits used in this paper virtually eliminate the substantial acquisition delay, and is also designed to free influence of 60 Hz zero crossing jitters which reside in a power signal. As a result, a PLM using a DS technique is realized in the form of wall-socket plug, and the PLM hardware would be very much simplified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.38-48
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• 1998

Generating test patterns for asynchronous sequential circuits remains to be a very difficult problem. There are few algorithms for this problem, and previous works cut feedback loops, and insert synchronous flip-flops in the feedback loops during ATPG. The conventional algorithms are similar to the algorithms for synchronous sequential circuits. This means that the conventional algorithms generate test patterns by modeling asynchronous sequential circuits as synchronous sequential circuits. So, test patterns generated by those algorithms nay not detect target faults when the test patterns are applied to the asynchronous sequential circuit under test. In this paper an algorithm is presented to generate test patterns for asynchronous sequential circuits. Test patterns generated by the algorithm can detect target faults for asynchronous sequential circuits with the minimal possibility of critical race problem and oscillation. And it is guaranteed that the test patterns generated by the algorithm will detect target faults.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.191-200
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• 2002

In this paper, we present the method transforming the interval functions into the truncated difference functions for multi-variable multi-valued functions and implementing the truncated difference functions to the multiple valued logic circuits with uniform patterns using the current mirror circuits and the inhibit circuits by current-mode CMOS. Also, we apply the presented methods to the implementation of circuits for additive truth table of 2-variable 4-valued MOD(4) and multiplicative truth table of 2-variable 4-valued finite fields GF(4). These circuits are simulated under 2${\mu}{\textrm}{m}$ CMOS standard technology, 15$mutextrm{A}$ unit current, and 3.3V power supply voltage using PSpice. The simulation results have shown the satisfying current characteristics. Both implemented circuits using current-mode CMOS have the uniform Patterns and the regularity of interconnection. Also, it is expansible for the variables of multiple valued logic functions and are suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.1-6
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• 2008

There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.