• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.685-688
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• 2006

A single-phase uninterruptible power supply system suitable for a SMES unit is proposed to achieve a simple circuit configuration and higher system reliability. It reduces the number of switching devices by applying a common-arm scheme. Operational principles to normal, stored-energy, and bypass mode are discussed in detail. Eliminating some of the switches or substituting passive components for active switches generally increases the sophistication and reduces degree of freedom in control strategy. However, the high-performance digital controller ran execute the complicated control task with no additional cost. The validity of the proposed UPS system will be verified by a computer-aided simulation.

• Journal of Power Electronics
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• v.15 no.2
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• pp.356-365
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• 2015

This paper presents a new single phase front-end ac-dc bridgeless power factor correction (PFC) rectifier topology. The proposed converter achieves a high efficiency over a wide range of input and output voltages, a high power factor, low line current harmonics and both step up and step down voltage conversions. This topology is based on a non-inverting buck-boost (Zeta) converter. In this approach, the input diode bridge is removed and a maximum of one diode conducts in a complete switching period. This reduces the conduction losses and the thermal stresses on the switches when compare to existing PFC topologies. Inherent power factor correction is achieved by operating the converter in the discontinuous conduction mode (DCM) which leads to a simplified control circuit. The characteristics of the proposed design, principles of operation, steady state operation analysis, and control structure are described in this paper. An experimental prototype has been built to demonstrate the feasibility of the new converter. Simulation and experimental results are provided to verify the improved power quality at the AC mains and the lower conduction losses of the converter.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.409-415
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• 2012

This paper presents a new software-based on-line dead-time compensation technique for a single-phase grid-connected photovoltaic (PV) inverter system. To prevent a short circuit in the inverter arms, a switching delay time must be inserted in the pulse width modulation (PWM) signals. This causes the dead-time effect, which degrades the system performance around zero-crossing point of the output current. To reduce the dead-time effect around the zero-crossing point of grid current, a harmonic mitigation of grid current is used as an additional part of the synchronous frame current control scheme. This additional task mitigates the harmonic components caused by the dead-time from the grid current. Simulation and experimental results are shown to verify the effectiveness of the proposed dead-time compensation method in the single-phase grid-connected inverter system.

• Journal of Power Electronics
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• v.18 no.1
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• pp.277-288
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• 2018

Wireless inductive power transfer (IPT) technology is used in many applications today. A compact and high-frequency primary side inverter is one of the most important parts of a WPT system. In this study, a modified class EF-type voltage-fed multi-resonant inverter has been proposed for WPT application at a frequency range of 85-100 kHz. Instead of an infinite input choke inductor, a resonant inductor is used to reduce loss and power density. The peak voltage stress across the MOSFET has been reduced to almost 60% from a class-E inverter using a passive clamping circuit. A simple yet effective design procedure has been presented to calculate the various component values of the proposed inverter. The overall system is simulated using MATLAB/SimPowerSystem to verify the theoretical concepts. A 500-W prototype was built and tested to validate the simulated results. The inverter exhibited 90% efficiency at nearly perfect alignment condition, and efficiency reduced gradually with the misalignment of WPT coils. The proposed inverter maintains zero-voltage switching (ZVS) during considerable load changes and possesses all the inherent advantages of class E-type inverters.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.749-752
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• 1993

This paper deals with the development of three phase 440[V], 500[KVA] Inverter system using the IGBT Devices. IGBT's have been used very successfully in variable frequency induction motor drive equipment. Problems associated with power devices characteristics when power devices are operated in parallel, such as balanced switching behavior and thermal stability, can be solved by using NPT type IGBT's. By Experimental results, it is confirmed that the voltage overshoot and reverse recovery current was very low. The equipment had proved to be reliable and short circuit proof. In addition, the performances in term of thermal characteristics, protection functions and stability are satisfactory.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1683-1693
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• 2017

This paper analyses the harmonic pollution to power grids caused by thyristor-controlled devices. It also formulates a mathematic derivation for the voltage spikes in thyristor-controlled branches to explain the harmonic and EMI derived from the reverse-recovery characteristics of the thyristor. With an equivalent nonlinear time-varying voltage source, a detailed simulation model is established, and the periodic dynamic switching characteristic of the thyristor can be explicitly implied. The simulation results are consistent with the probed results from on-site measurements. An improved trigger system with gate-shorted circuit structure is proposed to reduce the voltage spikes that cause EMI. The experimental results indicate that a prototype with the improved trigger system can effectively suppress the voltage spikes.

• Anxiety and mood
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• v.6 no.1
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• pp.31-36
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• 2010

Objective : Mismatch negativity (MMN) provides an electrophysiological index of an involuntary attention switching process. This study investigated MMN anomalies and their relationship to clinical variables in patients with obsessive-compulsive disorder (OCD). Methods : Study participants were 29 OCD patients and 24 normal controls. We used a 128-channel EEG to measure MMN during a passive oddball paradigm. Then we assessed the correlations between MMN amplitudes and clinical measures. Results : The OCD patients exhibited significantly greater MMN amplitude compared to the controls. Also, the right frontal lobe MMN amplitudes correlated significantly to the OCD patients' Yale-Brown Obsessive Compulsive Scale total scores (r=-0.520, p=0.005). Conclusion : These results suggest that MMN anomalies in OCD patients reflect a monitoring circuit dysfunction, raising the possibility that the OCD's pathophysiology includes glutamatergic dysfunction.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.161-166
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• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.112-119
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• 2021

This study proposes a design method of high-power-density and high-efficiency low-voltage DC-DC converters using SiC MOSFET and the optimized planar transformer design procedure based on the figure-of-merit. The secondary rectifying circuit of the phase-shifted full-bridge converter is compared to achieve high power density and high efficiency, and the phase-shifted full bridge converter with a current-doubler rectifier is selected. The planar transformer is designed by the proposed optimized design procedure and verified by FEA simulation. To validate the proposed design method, experimental results from a 3 kW prototype are provided. The prototype achieved 95.28% maximum efficiency and a power density of 2.98 kW/L.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1074-1086
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• 2019

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.