• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1063-1064
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• 2008

In this paper, two kinds of the protection circuits are proposed and simulated to verify their performances. One is an over current protection circuit, and the other is a no load protection circuit which reduces power consumption. These protection circuits of an LED drive circuit can reduce power consumption and prevent to damage the elements.

• Progress in Superconductivity and Cryogenics
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• v.18 no.2
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• pp.37-41
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• 2016

This paper presents the developed quench analysis code and protection circuit design for a superconducting magnet system of 28GHz electron cyclotron resonance (ECR) ion source. The superconducting magnet is composed of a hexapole magnet and four solenoid magnets located outside of the hexapole one. All magnets are wound with NbTi composite wire and impregnated by epoxy. By using the developed characteristic analysis code, the normal zone resistance, decaying current and temperature rising can be estimated during quench. Also, the stored magnetic energy is successfully consumed from the series resistor of the designed protection circuit. The analytical results are compared with the experimental results to verify the developed quench analysis code and protection circuit.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.136-144
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• 2004

From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.

• Journal of IKEEE
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• v.21 no.3
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• pp.234-239
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• 2017

In this paper, we propose an ESD (Electrostatic Discharge) protection circuit based on a new structure of SCR (Silicon Controlled Rectifier) embedded with PMOS structure. The proposed ESD protection circuit has a built-in PMOS structure and has a latch-up immunity characteristic and an improved tolerance characteristic. To verify the characteristics of the proposed ESD protection circuit and to analyze its operating characteristics, we compared and analyzed the characteristics of the existing ESD protection circuit using TCAD simulation. Simulation results show that the proposed protection ESD protection circuit has superior latch-up immunity characteristics like the existing SCR-based ESD protection device HHVSCR (High Holding Voltage SCR). Also, according to the results of the HBM (Human Body Model) maximum temperature test, the proposed ESD protection circuit has a maximum temperature value of 355K, which is about 20K lower than the existing HHVSCR 373K. In addition, the proposed ESD protection circuit with improved electrical characteristics is designed by applying N-STACK technology. As a result of the simulation, the proposed ESD protection circuit has a holding voltage characteristic of 2.5V in a single structure, and the holding voltage increased to 2-STACK 4.2V, 3-STACK 6.3V, 4-STACK 9.1V.

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.1-6
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• 2008

In this paper describes the process of designing a protection circuit against an open or short electronic ballast. An open electronic ballast creates high voltages in a regular period, which a lies voltage stress on switching devices. On the other hand, a shorted output generates excessive current, causing problems such as heat generation in the ballast and reduced lifespan of semiconductor devices. This study proposes a protection circuit consisting of TTL and passive devices to resolve the problems. The proposed protection circuit offers the benefits of low cost and high reliability. The proposed circuit was connected to an actual ballast to demonstrate its applicability.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.12
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• pp.589-595
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• 2004

The ESD protection characteristic of chip varistors on a circuit board can not be analyzed by using a conventional circuit simulator due to its microwave characteristic. Thus, by employing Agilent's microwave circuit simulator ADS, we showed that the ESD Protection characteristic or chip varistors can be investigated. order to got more precise simulation results, a chip varistor model was extracted from the electrical characteristic of a TDK's chip varistor and the distributed circuit based pattern was designed as the ESD propagation path. The simulation results showed that the ESD protection characteristic of a chip varistors can be improved drastically by reducing the ESD propagation path.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.96-101
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• 2012

A surge protection device of the metal oxide varistor(MOV) has been commonly used for preventing electrical damage in many electronic equipments. The MOV has a property that leakage current is increased and might be permanently damaged when it is exposed continuously to the electrical stresses such as lightening surges. In this paper, we propose a novel surge protection circuit adopting a silicon controlled rectifier(SCR) in the traditional protection circuits using the MOV device simultaneously. When lightning surges are injected to the proposed circuit, the MOV lets the surge pulses bypassing through the ground at first up to the level that SCR begins to operate. Above the threshold level of turning on the SCR, the SCR operates bypasses large surge currents to the ground. Proposed circuit was verified with a leakage current experiment and PSpice circuit simulations under the repeated surge injection environment.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.