• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.187-191
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• 2009

This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD ($1,920{\times}1,088$) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.399-400
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• 2008

This paper presents a new architecture of unified IP/IT/IQ/MC circuit for H.264 decoder based on operation sharing and efficient scheduling. The resultant circuit based on the proposed architecture uses only 12 adders and 1 multiplier. We further reduced the circuit size by sharing buffers. Our circuit consists of 47,810 gates and operates at the maximum operating frequency of 117MHz with 130nm standard cells.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.55-64
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• 2017

High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.48-54
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• 2010

This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1293-1296
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• 2008

As Flat Panel Display become large in format, the data and gate lines turn into longer, parasitic capacitance and resistance increase, and the display signal is delayed. Three dimensional architecture of multiplexing data registration integrated circuit method is used that divides the data line into several blocks and provides the advantages of high accuracy, rapid selection, and reasonable switching speed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1117-1120
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• 1998

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.114-114
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(f0= 100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPIC simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.