• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.8
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• pp.702-707
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• 2002

This paper presents a micro fluxgate sensor in printed circuit board (PCB). The fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a micro patterned amorphous magnetic ribbon and the core has a rectangular-ring shape. The amorphous magnetic core is easily saturated due to the low coercive field and closed magnetic path for the excitation field. Four outer layers as an excitation and pick-up coils have a planar solenoid structure. The chip size of the fabricated sensing element is 7.3$\times$5.7$\textrm{mm}^2$. Excellent linear response over the range of -100$\mu$T to +100$\mu$T is obtained with 540V/T sensitivity at excitation square wave of 3 $V_{p-p}$ and 360kHz. The very low power consumption of ~8mW was measured. This magnetic sensing element, which measures the lower fields than 50$\mu$T, is very useful for various applications such as: portable navigation systems, military research, medical research, and space research.h.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.59-64
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• 2022

Effects of film stack structure and peeling rate on the peel strength of screen-printed (SP) Ag/polyimide (PI) systems were investigated by a 90° peel test. When PI film was peeled at PI/SP-Ag and PI/SP-Ag/electroplated (EP) Cu structures, the peel strength was nearly constant regardless of the peeling rate. When EP Cu was peeled at EP Cu/SP-Ag/PI structure, the peel strength continuously increased as peeling rate increased. Considering uniaxial tensile test results of EP Cu/SP-Ag film with respect to loading rate, the increase of 90° plastic bending energy and peel strength was attributed to increased flow stress and toughness. On the other hand, viscoelastic PI film showed little variation of flow stress and toughness with respect to loading rate, which was assumed to result in nearly constant 90° plastic bending energy and peel strength.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.72-81
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• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.503-509
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• 2019

The demand for smaller, faster, and multi-functional mobile devices in increasing at a rapidly increasing rate. In response to these trends, Stacked Chip Scale Package (SCSP) is used widely in the assembly industry. A film type adhesive called die attach film (DAF) is used widely for bonding chips in SCSP. The DAF requires high flowability at high die attachment temperatures for bonding chips on organic substrates, where the DAF needs to feel the gap depth, or for bonding the same sized dies, where the DAF needs to penetrate bonding wires. In this study, the mixture design of experiment (DOE) was performed for three raw materials to obtain the optimized DAF recipe for low elastic modulus at high temperature. Three components are acrylic polymer (SG-P3) and two solid epoxy resins (YD011 and YDCN500-1P) with different softening points. According to the DOE results, the elastic modulus at high temperature was influenced greatly by SG-P3. The elastic modulus at $100^{\circ}C$ decreased from 1.0 MPa to 0.2 MPa as the amount of SG-P3 was decreased by 20%. In contrast, the elastic modulus at room temperature was dominated by YD011, an epoxy with a higher softening point. The optimized DAF recipe showed approximately 98.4% pickup performance when a UV dicing tape was used. A DAF crack that occurred in curing was effectively suppressed through optimization of the cure accelerator amount and two-step cure schedule. The imizadole type accelerator showed better performance than the amine type accelerator.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.12
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• pp.261-267
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• 2020

The demand for faster, lighter, and thinner portable electronic devices has brought about a change in semiconductor packaging technology. In response, a stacked chip-scale package(SCSP) is used widely in the assembly industry. One of the key materials for SCSP is a die-attach film (DAF). Excellent flowability is needed for DAF for successful die attachment without voids. For DAF with high flowability, two-step curing is often required to reduce a cure crack, but one-step curing is needed to reduce the processing time. In this study, DAF composition was categorized into three groups: cure (epoxy resins), soft (rubbers), hard (phenoxy resin, silica) component. The effect of the composition on a cure crack was examined when one-step curing was applied. The die-attach void and flowability were also assessed. The cure crack decreased as the amount of hard components decreased. Die-attach voids also decreased as the amount of hard components decreased. Moreover, the decrease in cure component became important when the amount of hard component was small. The flowability was evaluated using high-temperature storage modulus and bleed-out. A decrease in the amount of hard components was critical for the low storage modulus at 100℃. An increase in cure component and a decrease in hard component were important for the high bleed-out at 120℃(BL-120).

• The KIPS Transactions:PartC
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• v.11C no.4
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• pp.539-544
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• 2004

This paper presents the implementation of the bluetooth headset and the audio gateway connected to the mobile Phone in the embedded environment. The bluetooth module includes the BC02 processor chip, the BCSP02 firmware and the bluelab software Including bluetooth protocol stack. The above components in the bluetooth module developed at CSR company are used as the development environment. The application program using API functions supported by bluelab is coded by C language and loaded on the flash ROM of the bluetooth module. The cail processing capacity measuring the call setup time and the clearing time between the audio gateway and the headset is considered as the performance parameter of the developed systems. As a call setup and clearing time between the audio gateway and the headset is about 88.8ms, the call processing capacity is about 11 calls per second. Therefore the performance result is satisfied in the aspect of the call processing time.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.126-134
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• 2006

This paper describes the development of an embedded wireless LAN controller which can be in parallel operated with an existing utility controller. The embedded controller mainly consists of Prism(R) 2.5 chip set and Atmega 128 microcontroller. In order to communicate over the network, the controller including TCP/IP stack (IP, TCP, UDP, and ICMP), telnet, and X/Z modem has been developed. For a specific application, we have proposed an special method to convert data structure between TCP/IP and X/Z modem and a data buffer algorithm to minimize the RAM memory usage. Finally, the correctness and performance of the protocols are tested and verified using $CommView^{(R)}\;and\;DU^{(R)}$. The development is satisfactorily operated only for 3,381 bytes of RAM usage without sacrificing interoperability between hosts.