• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.4
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• pp.55-62
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• 2004

In this paper, we have developed a portable acceleration measurement system to measure acceleration signals during walking and a gait analysis algorithm which can evaluate gait regularity and symmetry and estimate gait parameters automatically. Portable acceleration measurement system consists of a biaxial accelerometer, amplifiers, lowpass filter with cut-off frequency of 16Hz, one-chip microcontroller, EEPROM and RF(TX/RX) module. The algerian includes FFT analysis, filter processing and detection of main peaks. In order to develop the algorithm, eight hemiplegic patients for training set and the other eight hemiplegic patients for test set are participated in the experiment. Acceleration signals during 10m walking were measured at 60 samples/sec from a biaxial accelerometer mounted between L3 and L4 intervertebral area. The algorithm, detected foot contacts and classified right/left steps, and then calculated gait parameters based on these informations. Compared with video data and analysis by manual, algorithm showed good performance in detection of foot contacts and classification of right/left steps in test set perfectly. In the future, with improving the reliability and ability of the algerian so that calculate more gait Parameters accurately, this system and algerian could be used to evaluate improvement of walking ability in hemiplegic patients in clinical practice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.141-148
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• 2004

Recently, the demand of broadband communications such as high-speed internet, HDTV, 3D-HDTV and ATM backbone network has been increased drastically. For transmitting the broad-bandwidth data using wireless network, it is needed to use ka-band frequency. However, the use of this ka-band frequency is seriously affected to the received data performance by rain fading and atmospheric propagation loss at the Ka-band satellite communication link. So, we need adaptive MODEM to endure the degraded performance by channel environment. In this paper, we will present the structure and design of the 155Mbps adaptive Modem adaptively compensated against channel environment. In order to compensate the rain attenuation over the ka-band wireless channel link, the adaptive coding schemes with variable coding rates and the multiple modulation schemes such as trellis coded 8-PSK, QPSK, and BPSK are adopted. And the blind demodulation scheme is proposed to demodulate without Information of modulation mode at the multi-mode demodulator, and the fast phase ambiguity resolving scheme is proposed. The design and simulation results of adaptive Modem by SPW model are provided. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the $0.25\mu{m}$ CMOS standard cell technology and 950 thousand gates.

• The KIPS Transactions:PartD
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• v.12D no.4 s.100
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• pp.543-552
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• 2005

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. The disk-based spatial indexing techniques, however, cannot direct apply to main memory databases, because the main purpose of disk-based techniques is to reduce the number of disk accesses. In main memory-based indexing techniques, the node access time is much faster than that in disk-based indexing techniques, because all index nodes reside in a main memory. Unlike disk-based index techniques, main memory-based spatial indexing techniques must reduce key comparing time as well as node access time. In this paper, we propose an efficient spatial index structure for main memory-based databases, called Tmr-tree. Tmr-tree integrates the characteristics of R-tree and T-tree. Therefore, Nodes of Tmr-tree consist of several entries for data objects, main memory pointers to left and right child, and three additional fields. First is a MBR of a self node, which tightly encloses all data MBRs (Minimum Bounding Rectangles) in a current node, and second and third are MBRs of left and right sub-tree, respectively. Because Tmr-tree needs not to visit all leaf nodes, in terms of search time, proposed Tmr-tree outperforms R-tree in our experiments. As node size is increased, search time is drastically decreased followed by a gradual increase. However, in terms of insertion time, the performance of Tmr-tree was slightly lower than R-tree.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.239-240
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• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• Journal of Life Science
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• v.19 no.8
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• pp.1159-1163
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• 2009

It has been postulated that endoplasmic (ER) stress is involved in the development of several diseases. However, the detailed molecular mechanisms have not been fully understood. Therefore, we characterized a genetic network of genes induced by ER stress using cDNA microarray and gene set expression coherence analysis (GSECA), and identified gene function as well as several transcription regulators associated with ER stress. We analyzed time-dependent gene expression profiles in thapsigargin-treated Sk-Hep1 using an oligonucleotide expression chip, and then selected functional gene sets with significantly high expression coherence which was processed into functional clusters according to the expression similarities. The functions related to sugar binding, lysosome, ribosomal protein, ER lumen, and ER to golgi transport increased, whereas the functions with mRNA processing, DNA replication, DNA repair, cell cycle, electron transport chain and helicase activity decreased. Furthermore, functional clusters were investigated for the enrichment of regulatory motifs using GSECA, and several transcriptional regulators associated with regulation of ER-induced gene expression were found.

• The KIPS Transactions:PartD
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• v.10D no.6
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• pp.1059-1066
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• 2003

In this paper, the magnetic sensing system is designed and implemented for the safe security in internet commerce system. When the payment is required inthe internet commerce system, the magnetic sensing system will get the information from a credit card without keyboard input and then encrypt and transmit the information to server. The credit card sensing system, which is proposed in this paper, is safe from keyboard hacking because it encrypts card information immediately in its internal chip and sends the information to host system. For the protection of information, the magnetic sensing system is basically based on a synchronous stream cipher cryptosystem which is related to a group of matrices. The size of matrices and the bits of keys for the best performances are determined for various cases. It is shown that for credit card payments. matrices of size 2 have good performance even at most 128bits keys with the consideration of inverse matrices. For authentication of general-purpose data, the magnetic sensing system needs more than 1.5KB data and in this case, the optimum size of matrices is 2 or 3 at more 256bits keys with consideration of inverse matrices.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Korean Journal of Remote Sensing
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• v.23 no.4
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• pp.297-309
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• 2007

The first Korean geostationary weather satellite, Communications, Oceanography and Meteorology Satellite (COMS) will be launched in 2008. The ground station for COMS needs to perform geometric correction to improve accuracy of satellite image data and to broadcast geometrically corrected images to users within 30 minutes after image acquisition. For such a requirement, we developed automated and fast geometric correction techniques. For this, we generated control points automatically by matching images against coastline data and by applying a robust estimation called RANSAC. We used GSHHS (Global Self-consistent Hierarchical High-resolution Shoreline) shoreline database to construct 211 landmark chips. We detected clouds within the images and applied matching to cloud-free sub images. When matching visible channels, we selected sub images located in day-time. We tested the algorithm with GOES-9 images. Control points were generated by matching channel 1 and channel 2 images of GOES against the 211 landmark chips. The RANSAC correctly removed outliers from being selected as control points. The accuracy of sensor models established using the automated control points were in the range of $1{\sim}2$ pixels. Geometric correction was performed and the performance was visually inspected by projecting coastline onto the geometrically corrected images. The total processing time for matching, RANSAC and geometric correction was around 4 minutes.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.604-609
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• 2019

In this study, we fabricated a capacitive humidity sensor with interdigitated (IDT) electrodes using a thermosetting polyimide as a humidifying material. First, the number of electrodes, thickness, and spacing of the polyimide film were optimized, and a mask was designed and fabricated. The sensor was fabricated on a silicon substrate using semiconductor processing equipment. The area of the sensor was $1.56{\times}1.66mm^2$, and the width of the electrode and the gap between the electrodes were each $3{\mu}m$. The number of electrodes was 166, and the length of an electrode was 1.294 mm for the sensitivity of the sensor. The sensor was then packaged on a PCB for measurement. The sensor was inserted into a chamber environment with a temperature of $25^{\circ}C$ and connected to an LCR meter to measure the change in capacitance at relative humidity (RH) of 20% to 90%, 1 V, and 20 kHz. The results showed a sensitivity of 26fF/%RH, linearity of < ${\pm}2%RH$, and hysteresis of < ${\pm}2.5%RH$.