• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.10-27
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• 2005

In this paper, we propose a high level design architecture of WCDMA(UMTS) base station modem and synchronization algorithms applied to the proposed architecture. Also analysis of each synchronization algorithm and performance evaluation of fixed point designed modem are shown. Since the target system is base station modem, each synchronization algorithm is designed for its stable operation. To minimize implementation complexity, optimum fixed point design for best operation of synchronization algorithms is performed. We performed symbol level link simulation with fixed point designed modem simulator for data rate of 12.2kbps, 64kbps, 144kbps, and 384kbps. We compared performance results to the minimum requirements specified in 3GPP TS 25.104(Release 5). Extensive computer simulation shows that the proposed modem architecture has stable operation and outperform the minimum requirement by 2 dB. The proposed modem architecture has been applied in the implementation of WCDMA reverse link receiver modem chip successfully.

• Journal of Magnetics
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• v.15 no.4
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• pp.213-220
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• 2010

Since the hypothalamus immediately reacts to a nerve by processing all the information from the human body and the external stimulus being conducted, it performs a significant role in internal secretion; thus, a diverse and rapid stimulus pulse is required. By detecting Zero Detector accurately via the application of AVR on-Chip (ATMEL) using commercial electricity, chopping generates a stimulus pulse to the brain using an IGBT gate to designate a new magnetic stimulation following treatment and diagnosis. To simplify and generate a diverse range of stimuli for the brain, chopping can be used as a free magnetic stimulator. Then, commercial frequency (60Hz) is chopped precisely at the first level of the leakage transformer to deliver an appropriate stimulus pulse towards the hypothalamus when necessary. Discharge becomes stable, and the chopping frequency and duty-ratio provide variety after authorizing a high-pressure chopping voltage at the second level of the magnetic stimulator. These methods have several aims. The first is to apply a variable stimulus pulse via accurate switching frequency control by a voltaic pulse or a pulse repetition rate, according to the diagnostic purpose for a given hypothalamus. Consequently, the efficiency tends to increase. This experiment was conducted at a maximum of 210 W, a magnetic induced amplitude of 0.1~2.5 Tesla, a pulse duration of $200{\sim}350\;{\mu}s$, magnetic inducement of 5 Hz, stimulus frequency of 0.1~60 Hz, and a duration of stimulus train of 1~10 sec.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Korean Journal of Materials Research
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• v.24 no.7
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• pp.351-356
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• 2014

A spherical $Sr_4Al_{14}O_{25}:Eu^{2+}$ phosphor for use in white-light-emitting diodes was synthesized using a liquid-state reaction with two precipitation stages. For the formation of phosphor from a precursor, the calcination temperature was $1,100^{\circ}C$. The particle morphology of the phosphor was changed by controlling the processing conditions. The synthesized phosphor particles were spherical with a narrow size-distribution and had mono-dispersity. Upon excitation at 395 nm, the phosphor exhibited an emission band centered at 497 nm, corresponding to the $4f^65d{\rightarrow}4f^7$ electronic transitions of $Eu^{2+}$. The critical quenching-concentration of $Eu^{2+}$ in the synthesized $Sr_4Al_{14}O_{25}:Eu^{2+}$ phosphor was 5 mol%. A phosphor-converted LED was fabricated by the combination of the optimized spherical phosphor and a near-UV 390 nm LED chip. When this pc-LED was operated under various forward-bias currents at room temperature, the pc-LED exhibited a bright blue-green emission band, and high color-stability against changes in input power. Accordingly, the prepared spherical phosphor appears to be an excellent candidate for white LED applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.619-624
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed (sequency divider has designed in a standard 0.25㎛ CMOS technology To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz a tuning range of $\pm$10%, and a gain of 154HHz/V. The simulated frequency synthesizer performance has a settling time of 1.5$\mu$s, a frequency range from 820MHz to IGHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of Astronomy and Space Sciences
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• v.19 no.4
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• pp.327-340
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• 2002

In this paper, we performed the design study of a wide-band digital autocorrelation spectrometer for the observation study of an extra-galaxy's spectral lines and the survey research of the special radio sources in field of the radio astronomy observational research. The autocorrelation spectrometer designed in this paper can be used to their spectrometer of any system because this spectrometer has a wide dynamic power and frequency range properties. In this system we use the aliasing sampling method to minimize the band loss. For the output signal of the correlator we can increase the signal processing speed using by a special DSP chip, the integration and the FFT using hardware, so this spectrometer can support the newest developed technique for the radio astronomy observation so called “On the fly” method.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.101-110
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• 2006

One of the most effective ways to improve cache performance is to exploit both temporal and spatial locality given by any program executional characteristics. This paper proposes a data cache with small space for low power but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block sire and a fully-associative buffer with large block size. To overcome the disadvantage of small cache space, two mechanisms are enhanced by considering operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes and an efficient block filtering to remove rarely reused data. The simulations on MediaBench show that the proposed 5KB-cache can provide equivalent performance and reduce energy consumption up to 40% as compared with 16KB 4-way set associative cache.