• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.991-992
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• 2006

Multiprocessor system is efficient and high performance architecture to overcome a limitation of single core SoC. In this paper, we propose a multiprocessor SoC (MPSoC) architecture which provides the low complexity and the high performance. The dynamic routing scheme has a serious problem in which the complexity of routing increases exponentially. We solve this problem by making a cluster with several PEs (Processing Element). In inter-cluster network, we use deterministic routing scheme and in intra-cluster network, we use dynamic routing scheme. In order to control the hierarchical network, we propose efficient router architecture by using smart crossbar switch. We modeled 2-D mesh topology and used simulator based on C/C++. The results of this routing scheme show that our approach has less complexity and improved throughput as compared with the pure deterministic routing architecture and the pure dynamic routing architecture.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.11
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• pp.1004-1011
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• 2016

In this paper, we suggested the methodology of analyzing and reconstructing of measured electromagnetic emanations from the Micro Controller Unit(MCU) chip of Universal Serial Bus(USB) keyboard. By analyzing electromagnetic emanations, entered information is found at keystroke and furthermore, information security problems such as personal information leakage and eavesdropping can be arisen. USB keyboards make the radiated signal according to the signal transmission mechanism. Electromagnetic emanations were measured by log periodic antenna and wideband receiver and were analyzed by signal processing algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1424-1428
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• 2004

In this paper, CMOS analog filters for use in the Analog front End of digital subscriber loop(DSL) chip set are proposed. Designed filters contain receiver continuous-time filters which are composed of lowpass and highpass functions. And their cutoff frequency are 138H1z and 1.1MHz respectively. A low-voltage gm-c integrator is improved and used to design filters. Desisned filters are verified by HSPICE simulation with the 0.25${\mu}m$ CMOS n-well parameter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2498-2507
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• 1994

This paper proposes the Doppler frequency tracking system by the optimum synchronization technique which compensates the frequency shifts caused by satellite movement in a coherent digital satellite communication system. A Doppler frequency shift caused by satellite movements and the design theories of the optimum synchronization system are mathematically described. Based on this theory, a Doppler frequency tracking system is implemented via digital signal processing techniques utilizing a DSP chip, RAMs, PROMs, and a 80286 microprocessor. The performance of the designed system was evaluated through the experiments with the INTELSATVA satellite.

• Journal of Magnetics
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• v.16 no.3
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• pp.246-252
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• 2011

A high-voltage power supply has been built for activation of the brain via stimulation using a Full Wave Cockroft-Walton Circuit (FWCW). A resonant half-bridge inverter was applied (with half plus/half minus DC voltage) through a bidirectional power transistor to a magnetic stimulation device with the capability of producing a variety of pulse forms. The energy obtained from the previous stage runs the transformer and FW-CW, and the current pulse coming from the pulse-forming circuit is transmitted to a stimulation coil device. In addition, the residual energy in each circuit will again generate stimulation pulses through the transformer. In particular, the bidirectional device modifies the control mode of the stimulation coil to which the current that exceeds the rated current is applied, consequently controlling the output voltage as a constant current mode. Since a serial resonant half-bridge has less switching loss and is able to reduce parasitic capacitance, a device, which can simultaneously change the charging voltage of the energy-storage condenser and the pulse repetition rate, could be implemented. Image processing of the brain activity was implemented using a graphical user interface (GUI) through a data mining technique (data mining) after measuring the vital signs separated from the frequencies of EEG and ECG spectra obtained from the pulse stimulation using a 90S8535 chip (AMTEL Corporation).

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.

• Journal of Institute of Control, Robotics and Systems
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• v.4 no.3
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• pp.384-391
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• 1998

When a device is mounted on the PCB, it is impossible to have zero defects due to many unpredictable problems. Among these problems, devices with bent corner leads due to mis-handling and which are not placed at a given point measured along the axis are principal problem in SMT(Surface Mounting Technology). It is obvious that given the complexity of the inspection task, the efficiency of a human inspection is questionable. Thus, new technologies for inspection of SMD(Surface Mounting Device) should be explored. An example of such technologies is the Automated Visual Inspection(AVI), wherein the vision system plays a key role to correct this problem. In implementing vision system, high-speed and high-precision are indispensable for practical purposes. In this paper, a new algorithm based on the Radon transform which uses a projection technique to inspect the FIC(Flat Integrated Circuit) device is proposed. The proposed algorithm is compared with other algorithms by measuring the position error(center and angle) and the processing time for the device image, characterized by line scan camera.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.367-370
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• 2002

In this paper, we propose a new node architecture LonWorh control Network for home network system environmint using power line communications. Using conventional Lon Work technology is a many disputable points for home network. LonWork network system needs high-cost development equipment. Moreover, conventional Lon Work system can not implement high-grade algorithms and variety application operation. because of the limitation of processing ability in Neuron chip. For that reason, the proposed structure is applicable to low-cost and more complex applications which are impossible in home network using conventional Lonworks structure. The proposed structure is implemented with some hardware and かone software for power line home network. The physical layer and the MAC layer of the LonTalk protocol within ton Work are implemented in hardware, which decreases the development costs communication processor. The upper of link layer of the LonTalk protocol is implemented with software, which decreases the development costs of software and increases the flexibility of tile system and increases the extension of the system. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network in home network. As a result, it is concluded that the proposed architecture provides increasing flexibility and decreasing cost of the system.