• Korean Journal of Environmental Agriculture
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• v.22 no.4
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• pp.261-265
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• 2003

In order to examine the difference in processing quality of potato tubers among localities, chemical properties of soils were analyzed and climatic conditions were investigated. Potatoes (Solanum tuberosum L.) were grown at seven localities of Korea during two years from 1994 to 1995. Soil samples and tubers were obtained from 2 to 3 commercial farms per locality with 10 days interval from 70 days before harvesting. As the result of that, higher correlation in processing quality was found with organic material content among soil conditions. On the climatic conditions, minimum temperature and sunshine hours during the period from 30 to 11 days before harvesting exhibited highly significant negative correlations with all quality parameters except reducing sugar content. Additionally, regression equations based on the observed level of these factors showed the relatively high coefficients of determination for dry matter content and chip color. To produce higher quality potatoes for processing, therefore, climatic conditions such as minimum temperature and sunshine hour and soil condition such as organic matter content have to be considered before the selection of areas or fields.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1025-1033
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• 2004

This paper covers the detection of covert direct sequence spread spectrum signal without the PN(Pseudo Noise) code information. Due to its low probability of interception, the difficulty of spectrum surveillance increases. Detection parameters are the signal existence of given bandwidth, the length of spreading sequence used by transmitter, and the identification of spreading code for detected chip length. The triple correlation function(TCF) value which is one of the higher order statistical signal processing techniques can be used to detect spread spectrum signal without a prior knowledge, but, it has weakness that TCF results depend on the spread data sequence in actual application. This paper proposes the new scheme that not only overcomes the weakness but also presents better performance than the traditional TCF scheme. The performance comparison of conventional TCF with proposed technique shows that the triple correlation estimator(TCE) has better detection capability.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.15-22
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• 2003

A film scanner is one of the input devices for ac acquiring high resolution and high qualify of digital images from the existing optical film. Recently the demand of film scanners have risen for experts of image printing and editing fields. However, due to the nonlinear characteristic of light source and sensor, colors of the original film image do not correspond to the colors of the scanned image. Therefore color correction for the scanned digital image is essential in film scanner. In this paper, neural network method is applied for the color correction to CIE L/sup *//a/sup *//b/sup */ color model data converted from RGB color model data. Also a film scanner hardware with 12 bit color resolution for each R, G, B and 2400 dpi is implemented by using the TMS320C32 DSP chip and high resolution line sensor. An experimental result shows that the average color correction rate is 79.8%, which is an improvement of 43.5% than our previous method, polygonal regression method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.493-502
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• 2009

In this paper, we compare the performance of initial timing acquisition in direct sequence ultra-wideband(DS-UWB) systems with different transmit pulse shaping filters through extensive computer simulations. Simulation results show that the timing acquisition performance of the DS-UWB system, whose chip rate is 1.32 Gchip/s, employing a rectangular transmit filter is similar to that employing a square root raised cosine(SRRC) filter with an interpolation factor of 4 in the realistic UWB channels(CM1 and CM3) as well as the additive white Gaussian noise(AWGN) channel. Additionally, we present both a 24-parallel digital correlator structure and a 24-parallel processing searcher operating at a 55 MHz system clock, and then briefly discuss the initial timing acquisition procedure. Because we can adopt an 1.32 Gsample/s digital-to-analog(D/A) converter and an 1.32 Gsample/s analog-to-digital(AID) converter in the DS-UWB system by employing the rectangular transmit filter, we have a realistic solution for the DS-UWB chipset development.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.87-94
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• 2006

For realizing an ubiquitous home network(uHome-net), various sensors should be able to be connected to an integrated wire/wireless sensor network. This paper describes an application case of applying LonWorks technology being widely used in control network to wire/wireless sensor network in uHome-net and the design and application of LonRF device that consists of a neuron chip including LonTalk protocol, a 433.92MHz RF transceiver, a sensor, and application programs. As an application example of the LonRF device, the LonRF smart badge that can measure the 3D location of objects in indoor environment and interwork with the uHome-net was developed. LonRF device based home network services were realized on the uHome-net testbed such as indoor positioning service, remote surveillance service and remote metering service were realized. This research shows that LonWorks technology based sensor network could be applicable to the control network in an ubiquitous home network and the LonRF device can be used as a wireless node in various sensor networks.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.23-34
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• 1997

A multi-channel digital GPS receiver has been developed including a RF-to-IF engine (engine 1), a digital signal processing engine (engine 2) with a microprocessor interfacing, and a navigation software. A high speed SiGe heterojunction bipolar transistor (HBT) as a active device has been mounted on chip-on-board (COB) type hybrid ICs such as LNA, mixer, and VCO in RF front-end of the engine 1 board. A 6-channel digital correlator together with a real-time clock and a microprocessor interface has been realized using an Altera Flex 10K FPGA as well as ASIC technology. Navigation software controlling the correlator for GPS signal tracking, retrieval and storing a message retrieval, and position calculation has been implemented. The GPS receiver was tested using a single channel STR2770 simulator. Successful navigation message retrieval and position determination was confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.6
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• pp.44-55
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• 2009

Diagnosis of diseases using gene expression data obtained from microarray chip is an active research area recently. It has been done by general machine learning algorithms, because it is difficult to analyze directly. However, recent research results about the analysis based on the interaction between genes is essential for the gene expression analysis, which means the analysis using the traditional machine learning algorithms has limitations. In this paper, we classify the gene expression data using the hyper-network model that considers the higher-order correlations between the features, and then compares the classification accuracies. And also, we present the new hypo-network model that improve the disadvantage of existing model, and compare the processing performances of the existing hypo-network model based on general sequential processor and the improved hypo-network model implemented on parallel processors. In the experimental results, we show that the performance of our model shows improved and competitive classification performance than traditional machine learning methods, as well as, the existing hypo-network model. We show that the performance is maximized when the hypernetwork model is implemented on our parallel processors.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.411-421
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• 2002

In this Paper we propose a new Image analysis algorithm for microarray processing and a method to locate the position of the grid cell using the topology of the grid spots. Microarray is a device which enables a parallel experiment of 10 to 100 thousands of test genes in order to measure the gene expression. Because of the huge data obtained by a experiment automated image analysis is needed. The final output of this microarray experiment is a set of 16-bit gray level image files which consist of grid-structured spots. In this paper we propose one algorithm which located the address of spots (spot indices) using graph structure from image data and a method which determines the precise location and shape of each spot by measuring the inclination of grid structure. Several experiments are given from real data sets.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.6
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• pp.11-17
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• 2001

Design and implementation of the MAC protocol processor prototype for high speed wireless LAN, which has interface with 5GHz OFDM PHY layer, is presented. We analyze the IEEE 802.11 MAC protocol specification and then separate the MAC protocol functions to be implemented by hardware and firmware and define the interface in which frames can be exchanged. That is, it is considered that high speed queue processing and interfaces with RISC processor and OFDM PHY layer. Protocol control and transmission/reception functions of the MAC functions are implemented in hardware in order to guarantee high speed processing in MAC layer. The developed MAC hardware block operates at 10MHz main clock. Therefore, transmission rate in PHY layer is about 80Mbps because data transmission/reception between MAC layer and PHY layer is performed as unit of octet. The designed FPGA MAC function chip has been implemented in wireless LAN test board and it is verified that DCF function is operated correctly.