• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1485-1487
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• 1987

To improve time delay produced in computation of trigonometric function by software method, the function generator was designed to compute the sine function with ROMs. Since the computation speed of trigonometric function can be improved by this ROM, it will be used in various parts required to scientific calculation-radar, FFT and signal processing etc.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.683-688
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• 1999

This paper describes design of equalizer chips of the read channel for high-density hard-disk drives. In order to meet increasing need of hard-disk drives, the read channel incorporates various PRML schemes. They require proper equalization to implement the efficient hardware of Viterbi decoders. This paper describes EPR-IV equalization for the read channel and a 200MHz analog FIR filter chip is presented which utilizes the sampled analog signal processing efficiently.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.88-138
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• 1996

Electronics grew up to the largest industry in the world supported by Si wafer. In near future, the Si wafer may use 300mm in diameter for economic requirement. This size wafer may use to produce large logic chip, 256Mbit DRAM, and other large complex and high density chip. Then, the quality including flatness and crustal characters may be required very high performance. And, their price should be reasonable and high quantity may be required. These requirements should be solve lot of hard problems of crystal growth, wafering mechanical processing and their cost problems. In this presentation, I may discuss following items.

• The Journal of the Acoustical Society of Korea
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• v.36 no.2
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• pp.123-129
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• 2017

In this paper, the realization of a directional digital hearing aid was considered. Conventional time domain time delay method was replaced with digital filters in order to make any general-purposed DSP (Digital Signal Processing) chip to produce the similar directivity pattern. Both the time delay algorithm and the digital filter algorithm were initially evaluated by Matlab (Matrix laboratory) for comparison, and it was confirmed by CSR 8675 Bluetooth DSP IC (Digital Signal Processing Integrated Circuit) chip firmware realization. Some remote control features by a smart phone was added to the smart hearing aid for user interface easiness.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.4
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• pp.30-36
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• 2004

The development of LD(Laser Diode) tester and its control system based on the graphical programming language(LabVIEW) is addressed. The ill tester is used to check the optic power and the optic spectrum of the LD Chip. The emitter size of LD chip and the diameter of the Detector(optic fiber and photo diode) are very small, therefore the test device needs high accuracy. But each motion part of the test device could not accomplish high accuracy due to the limit of the mechanical performance. So, an image processing with machine vision is proposed to compensate for the error. By adopting our method we can reduce the error of position within $\pm$5$\mu\textrm{m}$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.