• Journal of Applied Biological Chemistry
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• v.49 no.4
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• pp.143-147
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• 2006

A rapid PCR-based assay for detecting hepatitis B viral DNA(HBV DNA) in serum and plasma was developed using a new PCR instrument named GenSpector(TMC-1000, Samsung electronics). PCR was carried out using a chip-based platform, which enabled 50 PCR cycles with internal controls, and melting-curve analysis in 30 minutes. Verification of the amplified HBV DNA product and the internal control was based on specific melting temperatures(Tm) analysis, executed by the GenSpector software. Primers were designed within the region conserved through HBV genotypes A to F. The lower limit of detection was 840 copies/ml serum, conducted with serial dilutions of a HBV DNA positive control(ACCURUN 325 series 700, Boston Biomedica Inc.). The assay was also compared to another assay for HBV DNA(Versant HBV DNA 3.0 assay, Bayer HealthCare) for 200 samples(each 100 clinical negative and positive samples). The sensitivity and specificity were 100% matched. This rapid PCR-based assay is specific, reproducible, and enables qualitative detection of HBV DNA.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.93-100
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• 2008

In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

• BioChip Journal
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• v.12 no.4
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• pp.280-286
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• 2018

Hydrogel scaffolds composed of multiple components are promising platform in tissue engineering as a transplantation materials or artificial organs. Here, we present a new fabrication method for implementing multi-layered macroscopic hydrogel scaffold composed of multiple components by controlling height of hydrogel layer through precise control of ultraviolet (UV) energy density. Through the repetition of the photolithography process with energy control, we can form several layers of hydrogel with different height. We characterized UV energy-dependent profiles with single-layered PEGDA posts photocrosslinked by the modular methodology and examined the optical effect on the fabrication of multi-layered, macroscopic hydrogel structure. Finally, we successfully demonstrated the potential applicability of our approach by fabricating various macroscopic hydrogel constructs composed of multiple hydrogel layers.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1356-1366
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• 2011

The TPM(Trusted Platform Module) is a hardware chip to support a trusted computing environment. A rightful user needs a command authorization process in order to use principal TPM commands. To get command authorization from TPM chip, the user should perform the OIAP(Object-Independent Authorization Protocol) or OSAP(Object-Specific Authorization Protocol). Recently, Chen and Ryan alerted the vulnerability of insider attack on TPM command authorization protocol in multi-user environment and presented a countermeasure protocol SKAP(Session Key Authorization Protocol). In this paper, we simulated the possibility of insider attack on OSAP authorization protocol in real PC environment adopted a TPM chip. Furthermore, we proposed a novel countermeasure to defeat this insider attack and improve SKAP's disadvantages such as change of command suructures and need of symmetric key encryption algorithm. Our proposed protocol can prevent from insider attack by modifying of only OSAP command structure and adding of RSA encryption on user and decryption on TPM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.75-75
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• 2015

Strong interactions between electromagnetic radiation and electrons at metallic interfaces or in metallic nanostructures lead to resonant oscillations called surface plasmon resonance with fascinating properties: light confinement in subwavelength dimensions and enhancement of optical near fields, just to name a few [1,2]. By utilizing the properties enabled by geometry dependent localization of surface plasmons, metal photonics or plasmonics offers a promise of enabling novel photonic components and systems for integrated photonics or sensing applications [3-5]. The versatility of the nanoplasmonic platform is described in this talk on three folds: our findings on an enhanced ultracompact photodetector based on nanoridge plasmonics for photonic integrated circuit applications [3], a colorimetric sensing of miRNA based on a nanoplasmonic core-satellite assembly for label-free and on-chip sensing applications [4], and a controlled fabrication of plasmonic nanostructures on a flexible substrate based on a transfer printing process for ultra-sensitive and noise free flexible bio-sensing applications [5]. For integrated photonics, nanoplasmonics offers interesting opportunities providing the material and dimensional compatibility with ultra-small silicon electronics and the integrative functionality using hybrid photonic and electronic nanostructures. For sensing applications, remarkable changes in scattering colors stemming from a plasmonic coupling effect of gold nanoplasmonic particles have been utilized to demonstrate a detection of microRNAs at the femtomolar level with selectivity. As top-down or bottom-up fabrication of such nanoscale structures is limited to more conventional substrates, we have approached the controlled fabrication of highly ordered nanostructures using a transfer printing of pre-functionalized nanodisks on flexible substrates for more enabling applications of nanoplasmonics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.

• Journal of the Korea Institute of Military Science and Technology
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• v.20 no.6
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• pp.853-859
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• 2017

Terrorists always threats the global security with the possibility of using prohibited warfare, NBCs(Nuclear, Biological and Chemical Warfare). Compared to other prohibited warfares, most of biological warfare agents (BWAs) have no physical properties and time delays from spread to affect. Therefore the early detection is important to protect and decontaminate from BWAs. On the preliminary detection stage for suspicious material, most of detection kits only serve to know weather the BWAs exists or not. Due to this reason, simple field confirmation testing for suspicious substances have been used to identify materials which show negative result on detection kits. Considering the current Lab on a Chip(LOC) technologies, we suggest simple identification platform for unknown suspicious substances based on paper fluidics. We hope that our research will envision the future direction for the specific point-of-view for LOC technologies on detection strategy of BWAs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.