• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.9-17
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• 2007

This paper shows an implementation of the baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques are proposed to fulfill the mandatory requirements of the standard. For verification and analysis of this design, we use a Platform-based SoC (system on chip) environment. The entire system consists of test-board for the baseband processor chip and the SoC platform for implementing MAC (medium access control).

• Korean Chemical Engineering Research
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• v.54 no.2
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• pp.223-228
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• 2016

In this study, we described a simple and facile method to generate uniform microwells poly(dimethyl siloxane) (PDMS) microstamps through micro-molding for efficient, rapid and reliable cell patterning of adipocyte differentiation. In contrast to the conventional methods, the microstamp technologies are low expensive, non-toxic, and using a small amount of solution. Recently, Orlistat known as tetrahydrolipstatin is a prescription drug designed to treat obesity which is used to aid in weight loss and help to reduce overweight obesity. Here, 3T3-L1 cells were treated under various concentration manners of Orlistat $0.2{\mu}M{\sim}5.0{\mu}M$. and it was confirmed maximum 26.5% inhibition activity compared to control. Thus, we elucidated this platform can be used for the real-time analyzing of cell proliferation, adipocyte differentiation for evaluation of anti-obesity agents on cell chip. Furthermore, we except that this platform technology designed here might be readily be expanded to discover a wider variety of anti-obesity agents.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.503-506
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• 2015

In accordance with IoT(Internet of Things) commercialization, the need to design SoC-based hardware platform with wireless communication is increasing. This paper therefor proposes an SoC platform architecture with Smart Frame System inter-communicating between devices. Wireless communication functions and high-performance real-time image processing hardware structure was applied to existing digital photo frame. We developed a smart phone application to control the smart frame through Bluetooth communication. The SoC platform hardware consists of CIS controller, Memory controller, ISP(Image Signal Processing) module for image scaling, Bluetooth Interface for inter-communicating between devices, VGA/TFT-LCD controller for displaying video. The Smart Frame System to support the IoT services was implemented and verified using HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA. The operating frequency is 54MHz.

• Journal of Internet Computing and Services
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• v.9 no.6
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• pp.1-13
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• 2008

Trusted Computing is a hardware-based technology that aims to guarantee security for machines beyond their users' control by providing security on computing hardware and software. TPM(Trusted Platform Module), the trusted platform specified by the Trusted Computing Group, acts as the roots for the trusted data storage and the trusted reporting of platform configuration. Data sealing encrypts secret data with a key and the platform's configuration at the time of encryption. In contrast to the traditional data sealing based on binary hash values of the platform configuration, a new approach called property-based data sealing was recently suggested. In this paper, we propose and analyze a new property-based data sealing protocol using the weakest precondition concept by Dijkstra. The proposed protocol resolves the problem of system updates by allowing sealed data to be unsealed at any configuration providing the required property. It assumes practically implementable trusted third parties only and protects platform's privacy when communicating. We demonstrate the proposed protocol's operability with any TPM chip by implementing and running the protocol on a software TPM emulator by Strasser. The proposed scheme can be deployed in PDAs and smart phones over wireless mobile networks as well as desktop PCs.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.159-164
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• 2013

Recently the solution integrated of vision and motion controller which are important element in automatiomn system has been many developed. However typically such a solutions has a many case that integrated vision processing and motion control into network or organized two chip solution on one module. We implement one chip solution integrated into vision and motion controller using Zynq-7000 that is developed recently as extended processing platform. We also apply EtherCAT to motion control that is industrial Ethernet protocol which have compatibility for open standardization Ethernet in order to control of motion because EtherCAT has a secure to realtime control and can treat massive data.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.628-632
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• 2003

An intelligent miniature humanoid robot system is designed and implemented as a platform for researching walking algorithm. The robot system consists of a mechanical robot body, a control system, a sensor system, and a human interface system. The robot has 6 dofs per leg, 3 dofs per arm, and 2 dofs for a neck, so it has total of 20 dofs to have dexterous motion capability. For the control system, a supervisory controller runs on a remote host computer to plan high level robot actions based on the vision sensor data, a main controller implemented with a DSP chip generates walking trajectories for the robot to perform the commanded action, and an auxiliary controller implemented with an FPGA chip controls 20 actuators. The robot has three types of sensors. A two-axis acceleration sensor and eight force sensing resistors for acquiring information on walking status of the robot, and a color CCD camera for acquiring information on the surroundings. As an example of an intelligent robot action, some experiments on playing soccer are performed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.9
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• pp.3428-3434
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• 2010

In this paper, we proposed and implemented a quality measurement algorithm for IS-95 reverse-link signal. To measure the quality of the received signal, equalization, carrier frequency/phase offset estimation, and timing synchronization are essential. And, all signal processing are carried out with baseband signal. The equalizer works with 4-oversampled samples to remove ICI(InterChip Interference). The frequency/phase offset estimator is followed by timing synchronizer since it can work without aid of data and timing information. As the number of interpolation in timing synchronization increases, the measurement accuracy improves, but computation load increases simultaneously. Therefore, one need to choose adequately the number of interpolation regarding to the platform performance to be used for the proposed algorithm.

• Journal of Applied Biological Chemistry
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• v.49 no.4
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• pp.143-147
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• 2006

A rapid PCR-based assay for detecting hepatitis B viral DNA(HBV DNA) in serum and plasma was developed using a new PCR instrument named GenSpector(TMC-1000, Samsung electronics). PCR was carried out using a chip-based platform, which enabled 50 PCR cycles with internal controls, and melting-curve analysis in 30 minutes. Verification of the amplified HBV DNA product and the internal control was based on specific melting temperatures(Tm) analysis, executed by the GenSpector software. Primers were designed within the region conserved through HBV genotypes A to F. The lower limit of detection was 840 copies/ml serum, conducted with serial dilutions of a HBV DNA positive control(ACCURUN 325 series 700, Boston Biomedica Inc.). The assay was also compared to another assay for HBV DNA(Versant HBV DNA 3.0 assay, Bayer HealthCare) for 200 samples(each 100 clinical negative and positive samples). The sensitivity and specificity were 100% matched. This rapid PCR-based assay is specific, reproducible, and enables qualitative detection of HBV DNA.