• ETRI Journal
• /
• v.32 no.6
• /
• pp.969-971
• /
• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• Journal of electromagnetic engineering and science
• /
• v.11 no.3
• /
• pp.192-200
• /
• 2011

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.12
• /
• pp.1228-1235
• /
• 2014

Input impedance of UHF RFID tag chip is needed to design a tag. In determining the chip impedance, direct measurement method is adopted commonly. In this paper, problems generated from fixtures that interface between tag chip and coaxial-oriented measurement instrument are investigated and the result of the problems is shown, when the direct measurement method is applied. As an alternative to the method, a modeling method is proposed and its validity and accuracy are shown.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.75-79
• /
• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.1
• /
• pp.1-6
• /
• 2002

A new closed-form expressions to calculate frequency-dependent distributed inductance and the associated distributed series resistance of single interconnect on a lossy silicon substrate (CMOS technology) are presented. The proposed analytic model for series impedance is based on a self-consistent field method and the vector magnetic potential equation. It is shown that the calculated frequency-dependent distributed inductance and the associated resistance are in good agreement with the results obtained from rigorous full wave solutions and CAD-oriented equivalent-circuit modeling approach.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.11 s.353
• /
• pp.216-220
• /
• 2006

One of the approaches for reducing the size of the quarter wavelength monopole antenna is the helix and the stacked structure. This paper presents a formula for the relationship between the geometrical parameter and the operating frequency of a slacked helix chip antenna. The stacked helix chip antenna was designed for PCS/IMT-2000 dual-bands operation. The fabricated antenna uses an FR-4 substrate with relative permittivity of 4.2, and its dimensions are $15{\times}7.5{\times}0.4mm^3$. The measured impedance bandwidth (VSWR<2) is 400MHz at the operating frequency.