• ETRI Journal
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• 제32권6호
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• pp.969-971
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• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• Journal of electromagnetic engineering and science
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• 제11권3호
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• pp.192-200
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• 2011

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver.

• 한국전자파학회논문지
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• 제25권12호
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• pp.1228-1235
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• 2014

UHF RFID 태그를 설계하기 위해서는 태그 칩의 입력 임피던스 값이 필요하다. 입력 임피던스 산출에는 직접측정 방법이 보편적으로 사용되고 있다. 본 연구에서는 이 방법을 사용할 경우, 칩을 측정장치에 연결하기 위해 도입되는 픽스쳐에서 발생되는 문제점을 분석하고, 그 결과를 확인하였다. 이 문제를 근본적으로 피해갈 수 있는 대안으로 모델링 방법을 제안하고, 실험을 통해 타당성과 정확도를 확인하였다.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.1-6
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• 2002

A new closed-form expressions to calculate frequency-dependent distributed inductance and the associated distributed series resistance of single interconnect on a lossy silicon substrate (CMOS technology) are presented. The proposed analytic model for series impedance is based on a self-consistent field method and the vector magnetic potential equation. It is shown that the calculated frequency-dependent distributed inductance and the associated resistance are in good agreement with the results obtained from rigorous full wave solutions and CAD-oriented equivalent-circuit modeling approach.

• 대한전자공학회논문지TC
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• 제43권11호
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• pp.216-220
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• 2006

모노폴 안테나의 크기를 줄이기 위한 방법으로 헬릭스 형태로 변형하는 것과 적층형 구조를 사용하는 방법이 있다. 본 논문에서는 제안한 적층형 헬릭스 안테나의 구조 변수에 따른 동작 주파수의 관계식을 제안하였다. 그리고 구조 변수에 따른 동작 주파수의 변화 양상을 이용하여 PCS 와 IMT-2000 대역에서 동작하는 이중대역 적층형 헬릭스 칩 안테나를 제작하였다. 제작된 안테나는 유전율 4.2 를 갖는 FR-4 유전체를 사용하였고 면적은 $15{\times}7.5{\times}0.4mm^3$ 이다. 안테나의 적층을 위해 직경이 0.35mm 이고 높이가 0.4mm 인 비아 홀을 사용하였다. 측정한 대역폭(VSWR<2)은 약 400MHz이다.