• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.327-332
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• 2021

At the package level, semiconductor reliability inspections involves mounting a semiconductor chip package on a test socket. The form of the test socket is basically determined by the form of the chip package. It also acts as a medium to connect with test equipment through mechanical contact of the leads and socket leads in the chip package, and it minimizes signal loss in a signal transmission process so that an inspection signal can be delivered well to the semiconductor. In this study, a technique was applied to examine the interdependence of adjacent electrical transfer routes and the structure of adjacent electrical transfer paths. The goal was to enable short-circuit testing of fewer than 100 silicon test sockets through a single interface for life tests and precision measurements. The test results of the developed device show a test precision of 99% or more and a simultaneous test speed characteristic of 0.66 sec or less.

• Journal of the Korean Society for Precision Engineering
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• v.5 no.1
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• pp.40-49
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• 1988

The chip control problem is one of the important subjects to be studied in the metal cutting process. Especially, an important practical problem concerns the form of chips pro- duced in machining since this has important implications relative to : 1. Personal safety. 2. Possible damage to equipment and product. 3. Handling and disposal of swarf after machining. 4. Cutting forces, temperatures, and tool life. However, a dependable way to predict the form of chips in a wide range of cutting conditions has not been established satisfactorily. In this paper, the relationship between the form of chips and the ratios of cutting forces were studied experimentally. According to what the experiments have been carried out in the turning process the main results can be summarized as follows : 1. By use of the multiple linear regression model, emperical formulas which are suitable to wide ranges of cutting conditions with accuracy were obtained satisfactorily. 2. The correlations between the form of chips based upon the classification by Henriksen and the ratios of cutting forces, namely (feeding force/thrust force), (principal force/feeding force) were determined. 3. Using above results, the algorithms which predict the form of chips were constituted. With these algorithms, the form of chips in a wide range of cutting of cutting conditions can be predicted.

• Korean Journal of Materials Research
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• v.9 no.11
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• pp.1095-1101
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• 1999

Electroless Ni plating is applied to form bumps and UBM layer for flip chip interconnection. Characteristics of electroless Ni are also investigated. Zincate pretreatment is analyzed and plated layer characteristics are investigated according to variables like temperature, pH and heat treatment. Based on these observations, characteristics dependence to each variables and optimum electroless Ni plating conditions for flip-chip interconnection are suggested. Electroless Ni has 10wt% P, $60\mu\Omega$-cm resistivity, 500HV hardness and amorphous structure. It changes crystallized structure and hardness increases after heat treatment After interconnection of electroless Ni bumps by ACF flip chip method, we show their advantages and possibility in microelectronic package applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.459-461
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• 2022

One of the big differences between Network-on-Chip (NoC) and the existing parallel processing system based on an off-chip network is that data packet routing is performed using a centralized control scheme. In such an environment, the best-effort packet routing problem becomes a real-time assignment problem in which data packet arriving time and processing time is the cost. In this paper, the Hungarian algorithm, a representative computational complexity reduction algorithm for the linear algebraic equation of the allocation problem, is implemented in the form of a hardware accelerator. As a result of logic synthesis using the TSMC 0.18um standard cell library, the area of the circuit designed through case analysis for the cost distribution is reduced by about 16% and the propagation delay of it is reduced by about 52%, compared to the circuit implementing the original operation sequence of the Hungarian algorithm.

• Applied Microscopy
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• v.24 no.3
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• pp.87-93
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• 1994

In order to elucidate the machinability of lead brass, orthogonal machining experiment was conducted in SEM(Scanning Electron Microscope) equipped with a micro-machining device at a cutting speed of $7{\mu}m/s$ for brass containing 0.2 to 3wt% Pb. The microfactors (i.e., shear angle, contact length between chip and tool) were determined by in-situ observations. Machinability of brass containing lead is discussed in terms of the microfactors and the cutting resistant force tested by lathe cutting. The dynamic behavior of the chip formation of lead brass during the machining process was examined: The chips of lead brass form as a shear angle type. The shear angle increases with the content of lead in (6:4) brass. The pronounced effect of lead on the contact length between chip and tool was observed above 1% Pb. The cutting resistant force tested by lathe decreases remarkably with the lead content in brass. The observed microfactors are in close relation to the tested resistant force in macromachining.

• ETRI Journal
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• v.35 no.6
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1355-1360
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• 2005

In this paper, we approach the problem of image filter design automation using a kind of intrinsic evolvable hardware architecture. For the purpose of implementing the intrinsic evolution process in a common FPGA chip and evolving a complicated digital circuit system-image filter, the design automation system employs the reconfigurable circuit architecture as the reconfigurable component of the EHW. The reconfigurable circuit architecture is inspired by the Cartesian Genetic Programming and the functional level evolution. To increase the speed of the hardware evolution, the whole evolvable hardware system which consists of evolution algorithm unit, fitness value calculation unit and reconfigurable unit are implemented by a commercial FPGA chip. The Celoxica RC1000 card which is fitted with a Xilinx Virtex xcv2000E FPGA chip is employed as the experiment platform. As the result, we conclude the terms of the synthesis report of the image filter design automation system and hardware evolution speed in the Celoxica RC1000 card. The evolved image filter is also compared with the conventional image filter form the point of filtered image quality.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• Journal of the Korea Society of Computer and Information
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• v.6 no.4
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• pp.12-20
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• 2001

The problem of software bottle-neck may be arised from unbalance of demands and supply of software. This is caused from the fact that the capability of programmer could not be improved in software development. Therefor, the new method of software development should aim at improving the productivity of software. This paper presents the expressions to be the standardized software Program modules by means of the software chip. The expressions are consist of name, input, output, and iteration of each software chip. And they simple express a combination and separation in sequence, parallel, iteration, composition, mixing, and variety form. Therefore they can easily software reuse as a result of analyzing the flow of data clearly.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.18 no.5
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• pp.443-448
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• 2009

The roughness models have developed to describe the grinding behaviour and predict the final quality of workpiece. The model forms of the plunge grinding process are generally established with initial and steady state model form in accordance with the accumulated metal removal. The steady state roughness model form are based on the grinding condition and specific parameters are used to show the influence of it according to the grinding process such as the equivalent chip thickness and accumulated metal removal. However, the models have been developed in past are not considered the effect of changing the grinding conditions in the same batch. In this paper, the roughness model form to consider the effect of changing grinding condition is proposed and the performance of proposed model is evaluated based on the experimental results.