• 한국결정성장학회지
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• 제27권3호
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• pp.143-147
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• 2017

PVT법으로 성장된 AlN 단결정의 표면 특성 및 결정성을 신뢰성 있게 평가하기 위해 $KOH/H_2O_2$ 혼합액을 이용한 화학적 습식 에칭을 통하여 AlN 단결정의 결함을 분석하였고, 고온 어닐링 공정을 통해 단결정의 결정성 변화를 관찰하였다. $300^{\circ}C$ 이상의 고온에서 강 염기성의 etchant를 사용하는 기존 에칭 방법에서는 재료의 결정성에 따라 쉽게 over etching이 일어난다. Over etching이 일어날 경우 면적당 정확한 에치 핏의 개수를 알 수 없기 때문에 전위 밀도의 신뢰성이 매우 떨어진다. 따라서 이러한 단점을 보완하기 위해 KOH 수용액에 $H_2O_2$를 산화제로 사용하여 $100^{\circ}C$ 이하의 저온에서 에칭을 성공하였으며, 주사전자현미경(SEM, scanning electron microscope)을 통해 에치 핏을 관찰하여 최적 에칭 조건 및 전위 밀도를 확인할 수 있었다. 또한, 성장된 AlN 단결정에 고온 어닐링 공정을 적용한 후, DC-XRD(double crystal X-ray diffraction)를 이용하여 결정성을 평가한 결과, 고온 어닐링 공정 후 FWHM(full with at half maximum) 값이 급격히 감소되는 것을 확인하였으며 이에 대한 메커니즘을 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.199-205
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• 2006

Patterned sapphire substrates (PSS) were fabricated by a simple wet etching process with $SiO_2$ stripe masks and a mixed solution of $H_2SO_4$ and $H_3PO_4$. GaN layers were epitaxially grown on the PSS under the optimized 2-step growth condition of metalorganic vapor deposition. During the 1st growth step, GaN layers with triangular cross sections were grown on the selected area of the surface of the PSS, and in the 2nd growth step, the GaN layers were laterally grown and coalesced with neighboring GaN layers. The density of threading dislocations on the surface of the coalesced GaN layer was $2{\sim}4\;{\times}\;10^7\;cm^{-2}$ over the entire region. The epitaxial structure of near-UV light emitting diode (LED) was grown over the GaN layers on the PSS. The internal quantum efficiency and the extraction efficiency of the LED structure grown on the PSS were remarkably increased when compared to the conventional LED structure grown on the flat sapphire substrate. The reduction in TD density and the decrease in the number of times of total internal reflections of the light flux are mainly attributed due to high level of scattering on the PSS.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• 센서학회지
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• 제25권4호
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• pp.275-279
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• 2016

Chemical vapor deposited (CVD) polycrystalline graphene is widely used for various sensor application because of its extremely large surface-to-volume ratio. The electrical properties of CVD-graphene is significantly affected by the grain size and boundaries (GGBs), but evaluation of GGB of continuous monolayer graphene is difficult. Although several evaluation methods such as tunneling electron microscopy, confocal Raman, UV/ozone-oxidation are typically used, they still have issues in evaluation efficiency and accuracy. In this paper, we suggest an improved evaluation method for precise and simple GGB evaluation which is based on UV/ozone-oxidation and chemical etching process. Using this method, we could observe clear GGBs of CVD-graphene layers grown by different process conditions and statistically evaluate average grain sizes varying from $1.69{\sim}4.43{\mu}m$. This evaluation method can be used for analyzing the correlation between the electrical properties and grain size of CVD-graphene, which is essential for the development of graphene-based sensor devices.

• 한국전기전자재료학회논문지
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• 제30권3호
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• pp.185-191
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• 2017

Cadmium compounds with one dimension (1D) nanostructures have attracted attention for their excellent electrical and optical properties. In this study, vertically aligned CdTe-Si nanostructures with high density were synthesized by several simple chemical reactions. First, l D Te nanostructures were synthesized by silver assisted chemical Si wafer etching followed by a galvanic displacement reaction of the etched Si nanowires. Nanowire length was controlled from 1 to $25{\mu}m$ by adjusting etching time. The Si nanowire galvanic displacement reaction in $HTeO_2{^+}$ electrolyte created hybrid 1D Te-branched Si nanostructures. The sequential topochemical reaction resulted in $Ag_2Te-Si$ nanostructures, and the cation exchange reaction with the hybrid 1D Te-branched Si nanostructures resulted in CdTe-Si nanostructures. Wet chemical processes including metal assisted etching, galvanic displacement, topochemical and cation exchange reactions are proposed as simple routes to fabricate large scale, vertically aligned CdTe-Si hybrid nanostructures with high density.

• Bulletin of the Korean Chemical Society
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• 제34권11호
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• pp.3451-3455
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• 2013

Single-crystalline silicon nanowires (SiNWs) were fabricated by using an electroless metal-assisted etching of bulk silicon wafers with silver nanoparticles obtained by wet electroless deposition. The etching of SiNWs is based on sequential treatment in aqueous solutions of silver nitrate followed by hydrofluoric acid and hydrogen peroxide. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the Si substrate were produced. Free-standing SiNWs were then obtained using ultrasono-method in toluene. Alkyl-derivatized SiNWs were prepared to prevent the aggregation of SiNWs and obtained from the reaction of SiNWs and dodecene via hydrosilylation. Optical characterizations of SiNWs were achieved by FT-IR spectroscopy and indicated that the surface of SiNWs is terminated with hydrogen for fresh SiNWs and with dodecyl group for dodecyl-derivatized SiNWs, respectively. The main structures of dodecyl-derivatized SiNWs are wires and rods and their thicknesses of rods and wire are typically 150-250 and 10-20 nm, respectively. The morphology and chemical state of dodecyl-derivatized SiNWs are characterized by scanning electron microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.90.2-90.2
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• 2013

Vertically-aligned silicon nanostructure arrays (SNAs) have been drawing much attention due to their useful electrical properties, large surface area, and quantum confinement effect. SNAs are typically fabricated by chemical vapor deposition, reactive ion etching, or wet chemical etching. Recently, metal-assisted chemical etching process, which is relatively simple and cost-effective, in combination with nanosphere lithography was recently demonstrated for vertical SNA fabrication with controlled SNA diameters, lengths, and densities. However, this method exhibits limitations in terms of large-area preparation of unperiodic nanostructures and SNA geometry tuning independent of inter-structure separation. In this work, we introduced the layerby- layer deposition of polyelectrolytes for holding uniformly dispersed polystyrene beads as mask and demonstrated the fabrication of well-dispersed vertical SNAs with controlled geometric parameters on large substrates. Additionally, we present a new means of building in vitro neuronal networks using vertical nanowire arrays. Primary culture of rat hippocampal neurons were deposited on the bare and conducting polymer-coated SNAs and maintained for several weeks while their viability remains for several weeks. Combined with the recently-developed transfection method via nanowire internalization, the patterned vertical nanostructures will contribute to understanding how synaptic connectivity and site-specific perturbation will affect global neuronal network function in an extant in vitro neuronal circuit.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.687-692
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• 2011

Hafnium oxide ($HfO_2$) was very advantageous for substitute material of gate on existing transistor. $HfO_2$ has been widely studied due to high contact with polysilicon and thermal stability and also, it is easily etched by using HF solution. In this study, $HfO_2$ and thermal oxide films were etched by wet etch method using chemical etchant. Etch rate of $HfO_2$ and thermal oxide was linearly increased with increasing concentration of HF and temperature but etch rate of $HfO_2$ was higher than thermal oxide due to $H^+$, $F^-$, and $HF_2^-$ ions at below 0.5% concentration of HF. And also, etch selectivity was improved by adding Hydrazine as additive.

• Journal of Korean Vacuum Science & Technology
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• 제5권2호
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• pp.52-55
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• 2001

We report best dielectric function of ZnS by spectroscopic ellipsometry in the 3.7 - 6.0 eV photon energy range at room temperature. Using proper wet chemical etching procedure, natural overlayer was removed to obtain the pure dielectric function of ZnS, which had a higher <$\xi$$_2$> value at the El band gap peak than that previously reported. We also determined the dielectric property of the natural overlayer on ZnS by following the evolution of <$\xi$$_2$> with chemical etching. We found that the optical property of the overlayer was well described by amorphous semiconductor model.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.265.1-265.1
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• 2013

Nanoporous anodic aluminum oxide (AAO), a self-ordered hexagonal array has various applications for nanofabrication such as nanotemplate, and nanostructure. In order to obtain highly-ordered porous alumina membranes, Masuda et al. proposed a two-step anodization process however this process is confined to small domain size and long hours. Recently, alternative methods overcoming limitations of two-step process were used to make prepatterned Al surface. In this work, we confirmed that there is a specific tendency used a PDMS stamp to obtain a pre-patterned Al surface. Using the nanoindentaions of a PDMS stamp as chemical carrier for wet etching, we can easily get ordered nanoporous template without two-step process. This chemical etching method using a PDMS stamp is very simple, fast and inexpensive. We use two types of PDMS stamps that have different intervals (800nm, 1200nm) and change some parameters have influenced the patterning of being anodized, applied voltage, soaking and stamping time. Through these factors, we demonstrated the patterning effect of large scale PDMS stamp.