• Journal of the Korean Ceramic Society
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• v.35 no.5
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• pp.443-450
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• 1998

Layered double hydroxides(LDHs) [{{{{ {Mg }_{1-x } }}{{{{ {Al }_{x } }}({{{{ {OH}_{2 } }})]ζ+({{{{ {CO }`_{3 } ^{2- } ){ }_{x/2 } }}$.${{{{ { yH}_{2 }O }} wioth variation of layer charge densitywere synthesized by co-precipitation methdo since their charge densities have a very important role to be det-ermined the physicochemical properties of layered materials. The XRD IR and thermal studies of them were discussed and the kinetic study for the decarbonation reaction was also carried out. From the results of XRD analysis we found that the lattice parameter and the unit cell volume were linearly decreased with the amount of Al substituents(x) in the vicinity of x=2∼10${\times}$1/3${\times}$10-1 but they had nearly constant values when the x are far from these vicinit. The activation energies for the decarbonation reaction of x=6.8, 10${\times}$1/3${\times}${{{{ { 10}^{-1 } }} were estimated to be 47.0, 37.6, 39.3 kcal/mol The specific surface areas(90-120 m2/g) of stable hy-drotalcite-type LDHs were dractically decreased with increasing of layer charge density.

• Korean Journal of Environmental Agriculture
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• v.3 no.2
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• pp.50-54
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• 1984

For the development of slow releasing K-fertilizer, K-ion exchanged montmorillonite was evaluated and characterized by layer charge determination with n-alkylammonium method. By this method it was possible to discern inhomogenous charge distribution within the crystals and to estimate the upper and lower limit of the layer charge(layer charge limit for Young-il bentonite in Korea: ${\xi}=0.39-0.28$ $e/(SiAl)_4O_{10}$, ${\xi}=0.34$) and the mean value of interlayer cation exchange capacity of 0.915meq/100g.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.127-130
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• 1989

This paper reports the theoretical model and the experimental results regarding to the electrical conductivity of hydrogenated amorphous silicon (a-Si:H). The total effective conductance of a-Si:H with a planar structure has been considered as the sum of the conductance of an adsorbate-induced layer, a surface-interface layer, a bulk layer, and a substrate-interface layer. In order to investigate the effects of space charge layers in a-Si:H on the conductivity, the thickness dependence of the conductivity is characterized and the conductivities measured at the upper electrodes deposited on a-Si:H are compared with those measured at the lower electrodes deposited on the glass substrate. From our analysis, the bulk conductivity and the thickness of the space charge layer in a-Si:H are characterized quantitatively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Bulletin of the Korean Chemical Society
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• v.23 no.1
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• pp.71-74
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• 2002

The apparent barrier height for charge transfer through an interfacial water layer between a Pt/Ir tip and a gold surface has been measured using STM technique. The average thickness of the interfacial water layer inside an STM junction was controlled by the amount of moisture. A thin water layer on the surface was formed when relative humidity was in the range of 10 to 80%. In such a case, electron tunneling through the thin water layer became the majority of charge transfers. The value of the barrier height for the electron tunneling was determined to be 0.95 eV from the current vs. distance curve, which was independent of the tip-sample distance. On the other hand, the apparent barrier height for charge transfer showed a dependence on tip-sample distance in the bias range of 0.1-0.5 V at a relative humidity of approximately 96%. The non-exponentiality for current decay under these conditions has been explained in terms of electron tunneling and electrochemical processes. In addition, the plateau current was observed at a large tip-sample distance, which was caused by electrochemical processes and was dependent on the applied voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.409-417
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• 2003

We have studied electrical properties and luminous efficiency of organic light-emitting diodes(OLEDs) with different buffer layer and cathodes in a temperature range of 10 K and 300 K. Four different device structures were made. The OLEDs are based on the molecular compounds, N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine (TPD) as a hole transport, tris(8-hydroxyquinolinato) aluminum(III) (Alq$_3$) as an electron transport and omissive layer, and poly(3,4-ethylenedioxythiophene) :poly (styrenesulfonate) (PEDOT:PSS ) as a buffer layer. And LiAl was used as a cathode. Among the devices, the ITO/PEDOT:PSS/TPD/Alq$_3$/LiAl structure has a low energy-barrier height for charge injection and show a good luminous efficiency. We have got a highly efficient and low-voltage operating device using the conductive PEDOT:PSS and low work-function LiAl. From current-voltage characteristics with temperature variation, conduction mechanisms are explained SCLC (space charge limited current) and tunneling one. We have also studied energy barrier height and luminous efficiency at various temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.379-379
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• 2010

Recent technical advances in OLEDs (organic light emitting devices) requires more and more the improvement in low operation voltage, long lifetime, and high luminance efficiency. Inverted top emission OLEDs (ITOLED) appeared to overcome these problems. This evolved to operate better luminance efficiency from conventional OLEDs. First, it has large open area so to be brighter than conventional OLEDs. Also easy integration is possible with Si-based driving circuits for active matrix OLED. But, a proper buffer layer for carrier injection is needed in order to get a good performance. The buffer layer protects underlying organic materials against destructive particles during the electrode deposition and improves their charge transport efficiency by reducing the charge injection barrier. Hexaazatriphenylene-hexacarbonitrile (HAT-CN), a discoid organic molecule, has been used successfully in tandem OLEDs due to its high workfunction more than 6.1 eV. And it has the lowest unoccupied molecular orbital (LUMO) level near to Fermi level. So it plays like a strong electron acceptor. In this experiment, we measured energy level alignment and hole current density on inverted OLED structures for hole injection. The normal film structure of Al/NPB/ITO showed bad characteristics while the HAT-CN insertion between Al and NPB greatly improved hole current density. The behavior can be explained by charge generation at the HAT-CN/NPB interface and gap state formation at Al/HAT-CN interface, respectively. This result indicates that a proper organic buffer layer can be successfully utilized to enhance hole injection efficiency even with low work function Al anode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.665-671
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• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.