• 제목/요약/키워드: channel layers

검색결과 313건 처리시간 0.024초

A Study on Contact Resistance Reduction in Ni Germanide/Ge using Sb Interlayer

  • Kim, Jeyoung;Li, Meng;Lee, Ga-Won;Oh, Jungwoo;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권2호
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    • pp.210-214
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    • 2016
  • In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

An Analytical Model for Deriving the 3-D Potentials and the Front and Back Gate Threshold Voltages of a Mesa-Isolated Small Geometry Fully Depleted SOI MOSFET

  • Lee, Jae Bin;Suh, Chung Ha
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제12권4호
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    • pp.473-481
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    • 2012
  • For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

A hybrid numerical flux for supersonic flows with application to rocket nozzles

  • Ferrero, Andrea;D'Ambrosio, Domenic
    • Advances in aircraft and spacecraft science
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    • 제7권5호
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    • pp.387-404
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    • 2020
  • The numerical simulation of shock waves in supersonic flows is challenging because of several instabilities which can affect the solution. Among them, the carbuncle phenomenon can introduce nonphysical perturbations in captured shock waves. In the present work, a hybrid numerical flux is proposed for the evaluation of the convective fluxes that avoids carbuncle and keeps high-accuracy on shocks and boundary layers. In particular, the proposed flux is a combination between an upwind approximate Riemann problem solver and the Local Lax-Friedrichs scheme. A simple strategy to mix the two fluxes is proposed and tested in the framework of a discontinuous Galerkin discretisation. The approach is investigated on the subsonic flow in a channel, on the supersonic flow around a cylinder, on the supersonic flow on a flat plate and on the flow in a overexpanded rocket nozzle.

Application of Fuzzy Theory and Analytic Hierarchy Process to Evaluate Marketing Strategies

  • Yu, C.S.;Tzeng, G.H.;Li, H. L.
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 1998년도 The Third Asian Fuzzy Systems Symposium
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    • pp.352-357
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    • 1998
  • Conventional marketing research generally focuses on a single layer's benefit. A notable example is the consumer layer providing managers with partial market information to evaluate relevant strategies. As generally known, marketing management encounters complex supply and demand behaviors, thereby necessitation that a successful marketing strategy adopt multi-layer considerations, such as the consumer layer, channel-retailer layer, and marketing planner layer. In light of above situation, this study applies fuzzy theory and the analytic hierarchy process(AHP) technique to analyze the performances of marketing strategies under multi-layer benefits, In addition, conventional marketing research has difficulty in efficiently allocating the limited budget so that each desired criterion can be significantly enhanced by a group of events. Therefore, a weighting structure among the goal, layers, criteria, and strategies(i.e. a group of events) is also developed herein to trace the influential process and assist marketing managers in efficiently allocating resources(i.e.budget).

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Breakdown Characteristics for Insulation Design of HTS Transformer in Liquid Nitrogen

  • J.M. Joung;S.M. Baek;Kim, S.H.
    • 한국초전도ㆍ저온공학회논문지
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    • 제5권3호
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    • pp.38-42
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    • 2003
  • HTS transformer is promising one of HTS power applications to be commercialized in the near future. To realize the applications, insulation technology in the coolant, liquid nitrogen, should be established. So breakdown characteristics should be considered at insulation components; turn-to-turn, layer-to-layer, winding-to-winding, were investigated. Firstly breakdown strengths of Kapton films were compared with Kraft paper these are as turn insulator. And next the characteristics of surface flashover on FRP were measured and the influence on breakdown strength of bubble generated with joule heat was discussed with the shape of cooling channel between layers. Finally barrier effect at winding-to-winding was discussed.

초음파 영상 전달을 위한 ISDN(Integrated Service Digital-Network)의 LAPD(Link Access Procedure on the D-Channel) 프로토콜 구현에 관한 연구 (A Study on the Implementation of ISDN LAPD Protocol for the Ultrasonic Image Trasfer)

  • 정용길;한민수
    • 대한의용생체공학회:의공학회지
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    • 제14권4호
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    • pp.315-320
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    • 1993
  • This paper deals with a subject for implementation of L+ayer 1 and Layer 2(LAPD) of ISDN user-network interface on the basis of CCITT recommandation I.411, I.412, I.441 (Q.921), I.450(Q.930) and I.451 (Q.931) for ultrasonic image transfer. For the implementa tion of LAPD protocol of ISDN in this study. PC-CARD based hardware(TA :Terminal Adopt) is proposed and operating system (PC-XINU) supporting the Multiprocessing is transplanted to it. As the Service Access Point(SAP) is accessed by using the port of XINU and Layers which consist of transmitting and receiving part are independantly processed for each other in this proposed system. It can be easy and flexible to implement LAPD protocol for the message transfer.

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Organic thin-film transistors and circuits manufactured by sub-femtoliter inkjets

  • Someya, Takao;Sekitani, Tsuyoshi;Noguchi, Yoshiaki;Yokota, Tomoyuki;Klauk, Hagen;Zschieschang, Ute
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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    • pp.1229-1232
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    • 2008
  • We have successfully manufactured high-quality top-contact organic thin-film transistors using inkjet technologies with sub-femtoliter droplet volume. Silver fine lines were directly patterned by inkjet on pentacene channel layers. The minimum width of silver lines was $1{\mu}m$ with without the need for pre-patterning or surface pretreatments. The mobility was $0.3\;cm^2/Vs$.

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메탈-메탈 매트릭스 레이아웃 형태의 기능모듈 생성 (Functional Module Generation in Metal-Metal Matrix($M^3$) Layout Style)

  • 차영준;임종석
    • 전자공학회논문지A
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    • 제32A권1호
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    • pp.206-221
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    • 1995
  • Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.

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자기정렬 이중 리쎄스 공정에 의한 전력 MESFET 소자의 제작 (Power MESFETs Fabricated using a Self-Aligned and Double Recessed Gate Process)

  • 이종람;김도진;윤광준;이성재;강진영;이용탁
    • 전자공학회논문지A
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    • 제29A권2호
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    • pp.77-79
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    • 1992
  • We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

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A Novel Process for Fabricating High Density Trench MOSFETs for DC-DC Converters

  • Kim, Jong-Dae;Roh, Tae-Moon;Kim, Sang-Gi;Park, Il-Yong;Yang, Yil-Sulk;Lee, Dae-Woo;Koo, Jin-Gun;Cho, Kyoung-Ik;Kang, Young-Il
    • ETRI Journal
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    • 제24권5호
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    • pp.333-340
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    • 2002
  • We propose a new process technique for fabricating very high-density trench MOSFETs using 3 mask layers with oxide spacers and a self-aligned technique. This technique reduces the device size in trench width, source, and p-body region with a resulting increase in cell density and current driving capability as well as cost-effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3-2.4 ${\mu}m$ was 100 Mcell/$in^2$ and a specific on-resistance of 0.41 $m{\Omega}{\cdot}cm^2$ was obtained under a blocking voltage of 43 V.

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