• 대한전자공학회논문지TC
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• 제41권6호
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• pp.1-7
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• 2004

직접 변환 방식 수신기법은 SDR기반 미래 광대역 또는 다중 대역 무선통신 시스템을 위한 중요한 해의 하나로 인식되고 있다. 본 논문에서는 광대역의 대역폭을 가지면서도 시스템의 유연성을 극대화할 수 있도록 SDR기반 직접 변환 수신기에 적용가능한 I 및 Q 신호의 생성에 관하여 연구하였다. 먼저 실제의 SDR 기반 통신 환경을 고려한 직접 변환 SDR 시스템을 모델링하고, 수신기에서의 위상 오류의 영향을 분석하며 이에 따른 I/Q 채널의 준최적 재생 알고리즘을 제안하였다. 제안된 알고리즘은 실시간 early-late compensator 구조를 통하여 송신단과 수신단의 위상 오류를 실시간으로 보정하고 랜덤한 채널 잡음환경에서도 보다 안정된 성능을 유지하게 한다. 컴퓨터 시뮬레이션을 통하여, $45{\~}55$도의 랜덤 위상 오류가 난 경우, 제안된 시스템은 기존 시스템과 비교하여 약 4dB이상의 성능 개선이 있음을 확인하였다.

• 전자공학회논문지T
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• 제35T권1호
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• pp.7-13
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• 1998

Submicron급의 고집적 소자에서는 종래의 긴 채널 소자에서 생기지 않던 짧은 채널효과에 기인하는 2차원적인 영향으로 고온전자(hot carrier) 등이 발생하여 소자의 신뢰성을 저하시키는 요인이 되고 있어 이들의 발생을 최소화할 수 있는 다양한 형상의 소오스/드레인 구조가 연구되고 있다. 본 논문에서는 제작공정의 간략화, 소자규모의 미세화, 응답속도의 고속화에 적합한 소오스/드레인에 Schottky장벽 접합을 채택한 MOS형 트랜지스터를 제안하고, p형 실리콘을 이용한 소자의 제작을 통하여 동작특성을 조사하였다. 이 소자의 출력특성은 포화특성이 나타나지 않는 트랜지스터의 작용이 나타났으며, 전계효과 방식의 동작에 비하여 높은 상호콘덕턴스를 갖고 있는 것으로 나타났다. 여기서 고농도의 채널층을 형성하여 구동 전압을 낮게하고 높은 저항의 기판을 사용하므로서 드레인과 기판사이의 누설전류를 감소시키는 등의 개선점이 있어야 할 것으로 나타났다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권3호
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• pp.161-164
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• 2000

A simple methode for calculating the forward voltage drop of IGBTs is presented, on the voltage drops on the p+ body, the reverse biased depletion region between p+body and epi-layer, the epi layer, and the forward biased collector junction. The decrease of the total current density in the epi layer near the p+ body is taken into account. The proposed methode allows a simple but accurate determination of the forward voltage drop in IGBTs, avoiding the complex path taken in the previous model for the forward voltage drops on channel, accumulation region, and epi region. Numerical simulations for 1kV NPT-IGBT with a uniformly doped collector are shown to support the analytical results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.

• 한국농공학회:학술대회논문집
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• 한국농공학회 2002년도 학술발표회 발표논문집
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• pp.453-456
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• 2002

In this study, the effect of DEM resolution (15m, 30m, 50m, 70m, 100m, 200m, 300m) on the hydrological simulation was examined using BASINS (Better Assessment Science Integrating point and Nonpoint Source) for Heukcheon watershed (303.3km2) data from 1998 to 1999. Generally, as the cell size of DEM increased, topographical changes were observed as the original range of elevation decreased. The processing time of watershed delineation and river network needed more time and effort on smaller cell size of DEM. The larger DEM demonstrated had some errors in the junction of river network which might effects on the simulation of water quantity and quality. The area weighted average watershed slope became lower but the length weighted average channel slope became higher as the DEM size increased. DEM resolution affected substantially on the topographical parameter but less on the hydrological simulation. Considering processing time and accuracy on hydrological simulation DEM mesh size of 100m is recommended for this watershed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.104-109
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• 2008

A simple and efficient way of modeling backgating in GaAs MESFET's is presented through depletion width modulation of Schottky junction and channel-substrate interface. It is shown semi-empirically that such a modulation of depletion widths causes serious troubles in designing precision circuits since backgating drastically reduces threshold voltage of MESFET as well as drain current. Finally, some of the results are compared with reported experimental results. This model may serve as a starting point for rigorous characterization of backgating effect on various device parameters of GaAs MESFET's.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• 한국가시화정보학회:학술대회논문집
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• 한국가시화정보학회 2003년도 추계학술대회 논문집
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• pp.87-90
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• 2003

In this paper, flow characteristics of plasma flow in a micro-tube were investigated experimentally using Micro-PIV. For comparision, the experiments were repeated for DI-water instead of plasma. Both velocity profiles of Plasma and DI-water are well agreed with the theoretical velocity distribution of newtonian fluid. We also carried out generating plasma-in-oil droplet formation at a Y-junction microchannel. In order to clarify the hydrodynamic aspects involved in plasma droplet formation. Rhodamin B were mixed with plasma only for visualization of plasma droplet.