• Title/Summary/Keyword: cell delay

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A Study of Cell delay for ABR service in ATM network (ATM 네트워크에서 ABR 서비스의 셀 지연 방식에 관한 연구)

  • 이상훈;조미령;김봉수
    • Journal of the Korea Computer Industry Society
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    • v.2 no.9
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    • pp.1163-1174
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    • 2001
  • A general goal of the ATM(Asynchronous Transfer Mode) network is to support connections across various networks. ABR service using EPRCA(Enhanced Proportional Rate Control Algorithm) switch controls traffics in ATM network. EPRCA switch, traffic control method uses variation of the ACR(Allowed Cell Rate) to enhance the utilization of the link bandwidth. However, in ABR(Available Bit Rate) service, different treatments are offered according to different RTTs(Round Trip Times) of connections. To improve the above unfairness, this paper presents ABR DELAY mechanism, in which three reference parameters for cell delay are defined, and reflect on the messages of RM(Resource Management) cells. To evaluate our mechanism, we compare the fairness among TCP connections between ABR DELAY mechanism and ABR RRM mechanism. And also we execute simulations on a simple ATM network model where six TCP connections and a background traffic with different RTTs share the bandwidth of a bottleneck link. The simulation results, based on TCP goodput and efficiency, clearly show that ABR DELAY mechanism improves the fairness among TCP connections.

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Replica Technique regarding research for Bit-Line tracking (비트라인 트래킹을 위한 replica 기술에 관한 연구)

  • Oh, Se-Hyeok;Jung, Han-wool;Jung, Seong-Ook
    • Journal of IKEEE
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    • v.20 no.2
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    • pp.167-170
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    • 2016
  • Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

Cell Replacement Algorithm for Area Optimization (면적 최적화를 위한 셀 교체 알고리듬)

  • 김탁영;김영환
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.388-391
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    • 1999
  • This Paper presents an efficient algorithm that minimizes the area of the combinational system through cell replacement. During the minimization, it maintains the circuit speed same. For the minimization, the proposed algorithm defines the criticality of each cell, based on the critical delay and the number of paths passing through the cell. Then, it visits the cells of the system, one by one, from the one with the lowest criticality, and replaces it with the minimum area cell that satisfies the delay constraint. Experimental results, using the LGsynth91 benchmark circuits synthesized by misII, show that the proposed algorithm reduces the circuit area further by 17.54% on the average without sacrificing the circuit speed.

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Study on Call Admission Control in ATM Networks Using a Hybrid Neural Network. (하이브리드형 신경망을 이용한 ATM망에서의 호 수락제어에 관한 연구)

  • 김성진;서현승;백종일;김영철
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.94-97
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    • 1999
  • In this paper, a new real-time neural network connection admission controller is proposed. The proposed controller measures traffic flows, cell loss rate and cell delay periodically each classes. The Neural network learns the relation between those measured information and service quality by real-time. Also the proposed controller uses the DWRR multiplexer with buffer dedicated to every traffic source in order to measure the delay that cells experience in buffer. Experimental result shows that the proposed method can control effectively heterogeneous traffic sources with diverse QoS requirement.

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Handover Procedures and Analysis for Mobile IP in Macro cell (Macro cell에서 Mobile IP를 고려한 Handover 과정 및 분석)

  • 홍성화;노재성;정해원;조성준
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.277-280
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    • 2001
  • Due to the explosive popularization of the Internet, it has been researched for many mobile terminals how to receive various multimedia information. Especially, it has been considered that a mobile terminal is serviced with multimedia information through a inherent IP address. In this paper we have proposed the Handover Signaling Method and analyzed the Handover delay time of this proposed method in wireless section. This proposed method is appropriate to Broadband systems with Mobile IP. We have simulated Handover delay time with respect to the distance between a terminal and base stations

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Flow Control with Hysteresis effect in ATM Network (ATM망의 히스테리시스 특성을 이용한 흐름제어기법)

  • 정상국;진용옥
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.9
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    • pp.10-17
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    • 1994
  • In this paper, a priority schedling and a flow control algorithm with hysteresis effect are proposed for high-speed networks. A mathematical model for the flow control is proposed and a cell transition probability from this model is found. And the performance of the proposed algorithm is analyzed by a computer simulation. According to the simulation results, it can be shown that the priority scheduling and the flow control with hysteresis effect get the cell loss probability 0.061 better and the average delay 100ms better and the average delay 100ms beter than those of single threshold.

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Traffic analysis of the CDMA base station with repeaters using time delay devices (CDMA 시스템에서 Time Delay를 이용한 기지국과 중계기 Traffic 분석)

  • 조웅호;진용옥
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.9A
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    • pp.1348-1358
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    • 2000
  • The paper contributes to a traffic analysis for the CDMA cellular base station with repeater which are operated in a cell site. Usually the repeaters' traffic of the CDMA cellular system hardly could be separated from that of the base station because the links of the repeaters are divided from RF circuits of the base station. The paper introduces a traffic measuring method that separates the traffic of repeaters from that of the base station using time delay device. To get general results we use a single BTS(Base station Transceiver Subsystem) with three repeater as well as a single BTS with a single repeater. Then we proved that the traffic of the repeaters could separate from that of the base station clearly.

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VLSI Design for Automatic Magnetizing and Inspection System (자동착자 및 검사자동화 시스템을 위한 집적회로 설계)

  • Im, Tae-Yeong;Lee, Cheon-Hui
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.7
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    • pp.1929-1940
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    • 1999
  • In this paper a VLSI design for the automatic magnetizing and inspection system has been presented. This is a design of a peripheral controller, which magnetizes CRTs and computer monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a 0.8um CMOS SOG technology of ETRI. Most of the PPI functions have been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "linear delay predict model" was suggested in the LODECAP(LOgic DEsign CAPture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new " delay predict equation" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design. And we had descriptions on the other blocks of this system.

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Performance analysis of priority control mechanism with cell transfer ratio and discard threshold in ATM switch (ATM 스위치에서 폐기 임계치를 가진 셀전송비율 제어형 우선순위 제어방식의 성능 분석)

  • 박원기;김영선;최형진
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.3
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    • pp.629-642
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    • 1996
  • ATM switch handles the traffic for a wide range of appliations with different QOS(Quality-of-Service) requirements. In ATM switch, the priority control mechanism is needed to improve effectively the required QOS requirements. In this paper, we propose a priority control mechanism using the cell transfer ratio type and discard threshold in order to archive the cell loss probability requirement and the delay requirement of each service class. The service classes of our concern are the service class with high time priority(class 1) and the service class with high loss priority control mechanism, cells for two kind of service classes are stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the stored and processed within one buffer. In case cells are stored in the buffer, cells for class 2 are allocated in the shole range of the buffer and cells for class 1 are allocated up to discard threshold of the buffer. In case cells in the buffer are transmitted, one cell for class 1 is transmitted whenever the maximum K cells for class 2 are transmitted consecutively. We analyze the time delay and the loss probability for each class of traffic using Markov chain. The results show that the characteristics of the mean cell delay about cells for class 1 becomes better and that of the cell loss probability about cells for class 2 becomes better by selecting properly discard threshold of the buffer and the cell transfer ratio according to the condition of input traffic.

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Analysis of Cell Variation of ATM Transmission for the Poisson and MMPP Input Model in the TDMA Method (TDMA 방식에서 포아송 입력과 MMPP 입력 모델에 따른 ATM 전송의 셀 지연 변이 해석)

  • Kim, Jeong-Ho;Choe, Gyeong-Su
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.3
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    • pp.512-522
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    • 1996
  • To provide broadband ISDN service for the users in scattered locations, the application of satellite communications network is seriously considered. To trans mit ATM cells efficiently in satellite communications, it is effective to use TDM A method. However, it is necessary to have a method to compensate the cell delayvari-ation caused by the difference between TDMA and ATM. This paper optimized the cell control time(Tc) when traffic inputs have poisson or markov modulated poisson process by applying cell delay variation characteristics of time stamp method, which has the most advantages among compensation methods or cell delay variation. This paper also intorduces a method of reducing the cell clumping phenomena by adapting discrete time stamp method, including the analysis and evalutation of the range of required quality of CDV distribution by ATM transmission.The result of the experiment shows that CDV distribution-range can be controlled to 1.2$\times$Tc which reduces overall cell delay variation by discrrete time stamp method.

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