면적 최적화를 위한 셀 교체 알고리듬

Cell Replacement Algorithm for Area Optimization

This Paper presents an efficient algorithm that minimizes the area of the combinational system through cell replacement. During the minimization, it maintains the circuit speed same. For the minimization, the proposed algorithm defines the criticality of each cell, based on the critical delay and the number of paths passing through the cell. Then, it visits the cells of the system, one by one, from the one with the lowest criticality, and replaces it with the minimum area cell that satisfies the delay constraint. Experimental results, using the LGsynth91 benchmark circuits synthesized by misII, show that the proposed algorithm reduces the circuit area further by 17.54% on the average without sacrificing the circuit speed.