• Journal of electromagnetic engineering and science
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• 제16권1호
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• pp.57-65
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• 2016

In this paper, based on the mode analysis of four-conductor lines, the extended mixed-mode chain-parameters and S-parameters of four-conductor lines are estimated using current division factors. The extended mixed-mode chain-parameters of cascaded four-conductor lines are then obtained with mode conversion. And, the extended mixed-mode S-parameters of cascaded four-conductor lines can be predicted from the transformation of the extended chain-parameters. Compared to the extended mixed-mode S-parameters of four-conductor lines, the cross-mode S-parameters are induced in the extended mixed-mode S-parameters of cascaded four-conductor lines, due to the imbalanced current division factors of cascaded two sections. The generated cross-mode S-parameters make the equivalent different- and common-mode conductors not independent from each other again. In addition, a new mode conversion, which applies the imbalanced current division factors, between the extended mixed-mode S-parameters and standard S-parameters is also proposed in this paper. Finally, the validity of the proposed extended mixed-mode S-parameters and mode conversion is confirmed by a comparison of the simulated and estimated results of shielded cable.

• 정보처리학회논문지C
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• 제11C권1호
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• pp.31-38
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• 2004

이동 에이전트 환경에서는 에이전트의 이동성으로 인하여 에이전트의 이주(migration)가 연속적으로 발생할 수 있다. 이에 따라 에이전트를 실행한 권한을 위임(delegation)하기 위해 플레이스(Place)간에 연속위임(cascaded delegation)이 발생할 수 있다. 기존의 연구는 에이전트 이주에 관련한 두 플레이스만을 위임의 대상으로 고려하기 때문에 안전한 연속 위임을 지원하지 않는다. 본 연구에서는 이동 에이전트 환경에서 연속 위임을 안전하게 수행하는 연속 위임 구현 기법을 제안한다. 제안 기법은 플레이스간의 신뢰관계에 따라 각 위임토큰(delegation token)을 다음에 생성되는 위임토큰에 내포시킨 후 서명하는 방법과 에이전트의 생성자에 의해 서명된 초기 토큰(initial token)만을 내포시킨 후 서명하는 방법을 나눠서 사용한다. 또한 본 제안 기법이 메시지 재연에 의한 공격과 위임토큰 치환 공격에 안전함을 증명한다.

• 전기학회논문지
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• 제62권4호
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• Journal of Power Electronics
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• 제14권1호
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• Journal of Power Electronics
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• 제12권4호
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• pp.567-577
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• 2012

This paper introduces a new scheme to balance the DC bus voltages of a cascaded H-bridge converter which is used as a Distribution Static Synchronous Series Compensator (D-SSSC) in electrical distribution network. The aim of D-SSSC is to control the power flow between two feeders from different substations. As a result of different cell losses and capacitors tolerance the cells DC bus voltage can deviate from their reference values. In the proposed scheme, by individually modifying the reference PWM signal for each cell, an effective balancing procedure is derived. The new balancing procedure needs only the line current sign and is independent of the main control strategy, which controls the total DC bus voltages of cascaded H-bridge. The effect of modulation index variation on the capacitor voltage is analytically derived for the proposed strategy. The proposed method takes advantages of phase shift carrier based modulation and can be applied for a cascaded H-bridge with any number of cells. Also the system is immune to loss of one cell and the presented procedure can keep balancing between the remaining cells. Simulation studies and experimental results validate the effectiveness of the proposed method in the balancing of DC bus voltages.

• Journal of Power Electronics
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• 제10권1호
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• pp.97-105
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• 2010

This paper presents the modeling, control and simulation of an interconnection system (ICS) of cascaded distributed generation (DG) modules for both grid-tied and stand-alone operations. The overall configuration of the interconnection system is given. The interconnection system consists of a cascaded DC/DC boost converters and a DC/AC inverter. Detailed modeling of the interconnection system incorporating a cascaded architecture has not been considered in previous research. In this paper, suitable control systems for the cascaded architecture of power electronic converters in an interconnection system have been studied and modeled in detail. A novel control system for DC/DC boost converters is presented based on a droop voltage controller. Also, a novel control strategy for DC/AC inverters based on the average large signal model to control the aggregated DG modules under both grid-tied and stand-alone modes is demonstrated. Simulation results indicate the effectiveness of the proposed control systems.

• 전력전자학회논문지
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• 제17권6호
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• pp.471-477
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• 2012

In this paper, in order to use module integrated converter using cascaded buck-boost converter for a low battery charger in stand-alone system, a charging algorithm which considers photovoltaic and battery status and PWM controllers which are changed according to charging modes are proposed. The proposed algorithm consists of constant current mode, constant voltage mode and maximum power point tracking mode which enables the battery to charge with maximum power rate. This paper also presents design of cascaded buck-boost converter that is the photovoltaic charger system. A 150W prototype system is built according to verify proposed the charger system and the algorithm.

• 대한전자공학회논문지SP
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• 제39권1호
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• pp.87-96
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• 2002

본 논문에서는 소프트웨어 라디오 수신기의 programmable down converter(PDC) 구현을 위한 효율적인 데시메이션 필터 구조를 제안한다. 제안된 데시메이션 필터는 개선된 cascaded integrator-comb(CIC)필터, cascaded comb, modified halfband 필터 및 halfband 필터, 프로그램 가능한 FIR 필터로 이루어져 있다. 새롭게 제안된 구조는 보상필터를 사용하여 CIC 필터의 통과대역 주파수 감쇠를 보완하고 aliasing억제 능력을 높여, CIC 필터에서 더욱 많은 데시메이션을 담당하도록 설계되었다. 또한 CIC의 보상필터로 인해 cascaded comb 및 modified halfband 필터를 사용 가능토록 하였다. 이러한 구조는 곱셈기가 필요 없기 때문에 연산량을 줄일 수 있고, FIR 필터의 계수를 줄일 수 있다. 실제 구현에서는 기존의 해리스사의 하드웨어에 비해, 곱셈 연산시 연산자 개수는 약 20%, 연산량은 약 50%의 복잡도를 줄일 수 있었다.

• Journal of Power Electronics
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• 제16권2호
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• pp.490-497
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• 2016

The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

• Journal of Power Electronics
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• 제16권5호
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• pp.1763-1772
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• 2016

To reduce system complexity and implementation costs, fully-controlled H-bridge (FHB) modules and diode H-bridge PFC (DHB) modules are cascaded to form a hybrid cascaded H-bridge rectifier (HCHR). In this paper, the advantages of such a HCHR over other cascaded rectifiers are analyzed depending on the numbers of FHB modules and DHB modules. Therefore, to assign proper numbers to these two kinds of modules for the HCHR, a configuration determination method is investigated under balanced and imbalanced loads. Three principles are also presented to guide the configuration determination for the HCHR. In addition, the constraints for selecting the step-up ratio and filter inductance are derived based on a phasor diagram analysis. The proposed configuration determination method is validated by simulations under three different conditions in the PSIM environment. Finally, experiments are carried out on a scaled-down prototype where the configuration can be easily adjusted. The feasibility of the proposed theory is then verified by experimental results.