• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.05a
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• pp.357-361
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• 2003

According to the remarkable reduction of the vehicle noise, the important of tire noise which is generated from the vehicle and the necessities of the researches for the noise reduction are emphasized. In this study, we have studied the road noise which is excited by the interaction between tire and road. In order to evaluate the road noise, we carry out the subjective test(feeling test). In order to consider the effect of the vehicle suspension for the tire/road noise, we are equipped with identical tires on the differential vehicle suspension and evaluate the road noise. In order to consider the effect of the tire structure for the tire/road noise, we evaluate the some tires with various structures. From the test results, we fine that the difference of road noise is generated by the variation of the vehicle suspension. Also, we can select the optimized tire structure which can be reduced the road noise.

• Communications for Statistical Applications and Methods
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• v.12 no.2
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• pp.483-496
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• 2005

We consider the power law process which is assumed to have multiple changepoints. We propose a binary segmentation procedure for locating all existing changepoints. We select one model between the no-changepoints model and the single changepoint model by the Bayes factor. We repeat this procedure until no more changepoints are found. Then we carry out a multiple test based on the Bayes factor through the intrinsic priors of Berger and Pericchi (1996) to investigate the system behaviour of failure times. We demonstrate our procedure with a real dataset and some simulated datasets.

• Proceedings of the Korean Reliability Society Conference
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• 2005.06a
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• pp.349-355
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• 2005

The bolts used for the electronic parts of a car a is the important parts which carry out an electric and physical performance. At the time of storage, transportation and use, Corrosion occurs in bolts under the influence of environmental factor. During the period exported especially overseas the chemical corrosion by the chlorine ion contained in the atmosphere occurs frequency. Then, The failure mechanism over corrosion is investigated and we consider to the design procedure of a environmental examination. We are going to select the proper plating thickness of bolts through a salt spray test, for investigating the corrosion resistance of bolts.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.367-370
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• 2017

This paper proposes a method for selecting efficient relay nodes in stochastic DTN model. Delay Tolerant Network (DTN) uses the Carry and Forward method, which creates a bundle layer for efficient communication, selects relay nodes between different networks and heterogeneous networks, and forwards messages. DTN is basically composed of mobile nodes so DTN has no fixed routing route and it has long latency due to intermittent connection. Therefore, the nodes constituting the DTN necessarily have the characteristics to store the messages, and the capacity of the stored messages and nodes affects the performance of the network. Stochastic DTN model proposed a Markov model that changes randomly over time to analyze the performance of DTN. In this paper, we use stochastic message distribution and node contact probabilities using contact time analyzed through message generation and extinction in order to select efficient relay nodes in stochastic DTN model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.47 no.9
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• pp.678-685
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• 2019

Due to the changes in future war environment and the technological development of the aviation weapon system, it is required to carry out on the analysis of the Manned-Unmanned aerial vehicles Teaming(MUM-T). Conventional manned-unmanned aerial vehicles operate according to the air strategy missions and vehicles' performance. In this paper, we analyze conventional aerial vehicle's mission to derive various kinds of missions of MUM-T after analyzing the unmanned aircraft systems roadmap issued by US DoD and the air strategy of US Air Force. Next, we identify the basic operations of the vehicles to carry out the missions, select the MUM-T based Suppression of Enemy Air Defense missions(SEAD), and analyze the procedure for performing the missions step by step. In this paper, we propose a procedure of the mission in the context of physical space and timeline for the realization of the concept of MUM-T.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.59-66
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• 2000

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2609-2614
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• 2007

Shell & Tube type Oil Cooler is widely used for hydraulic presses, die casting machines, generation equipments, machine tools and construction heavy machinery. Temperature of oil in the hydraulic system changes viscosity and thickness of oil film. They have a bad effect to performance and lubrication of hydraulic machinery, so it is important to know exactly the heat exchanging efficiency of oil cooler for controlling oil temperature. But most Korean manufacturers do not have test equipment for oil cooler, so they cannot carry out the efficiency test of oil cooler and it is impossible to verify its performance. This paper includes information of construction of necessary utilities for oil cooler test and design and manufacture of test equipment. One can select the optimum product by obtaining performance data through tests of various kinds of oil coolers. And also the paper developed a program which can be easily used for design of 2D and 3D drawings of oil cooler.