• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1203-1205
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• 2007

Confinement of charge carrier and exciton is the essential factor for enhancing the efficiency and stability of the electrophosphorescent devices. The interplay between the properties of emitters and other adjacent layers are studied based on the physical interpretation with difference of energy level, charge carrier mobility, and corresponding charge-trapping behavior.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.292-295
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• 2002

In this work, transient characteristics of NPT(Non Punch Through)-IGBT(Insulated Gate Bipolar Transistor) have been studied with different temperatures analytically. Power losses are caused by heat generated in MIT-IGBT for steady state and transient state conditions. We therefore have focused on the analysis of excess carrier concentration and excess charge injected into N-drift layer with different temperatures and have obtained anode voltage drop during turn-off with lifetime of 2.4[${\mu}$s].

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 추계학술대회 논문집
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• pp.103-103
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• 2008

• 한국응용과학기술학회지
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• 제32권1호
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• pp.1-6
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• 2015

본 연구에서는 발광층의 전자와 정공의 재결합 영역을 확인하고, 단계적 도핑구조를 이용하여 여기자들의 효율적인 분배를 통해 roll-off 효율을 감소시켜서 녹색 인광 유기발광다이오드의 수명 증가를 나타냈다. 발광층 내 호스트는 양극성의 4,4,N,N'-dicarbazolebiphenyl (CBP)를 사용하여 전하의 이동을 원활하게 하였다. 발광층을 네 구역으로 분할하여 각각 소자를 제작하였고, 네 구역의 도판트 농도에 따라 발광효율과 수명 향상을 보였다. 이로써 발광층 내의 단계적 도핑구조를 이용하여 캐리어와 여기자들이 원활하게 분배된 것을 확인하였다. 기준소자 대비 발광층의 도판트 농도를 5, 7, 11, 9% 순서로 단계적 도핑구조를 적용한 device C의 수명이 약 73.70% 증가하였고, 휘도 효율은 51.10 cd/A와 외부 양자 효율은 14.88%의 성능을 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.844-847
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• 2001

In this work, transient characteristics of the Non-Punch Through(NPT) Insulated Gate Bipolar Transistor(IGBT) has been studied. we has analyzed with lifetimes excess minority carrier injected into N-dirft, base region of IGBT's BJT part and accumulated charge of on-state which affected swiching characteristic. In this paper, excess minority carrier and charge distribution in active base region is expressed analytically. This analysis proposed optical trade-off between lifetimes and accumulated charge for decreasing switching losses because charge result in switching loss when device was tuned off.

• 전자공학회논문지A
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• 제31A권1호
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.

• 한국컴퓨터정보학회논문지
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• 제9권1호
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• pp.9-15
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• 2004

본 논문에서는 드레인 부근의 채널 영역에서 접합 전계를 줄이는 WSW(Wrap Side Wall) 구조의 소자를 제안하였다. WSW구조의 소자 제작은 첫 번째 게이트를 식각한 후에 NM1(N-type Minor1) 이 온주입을 하고 다시 질화막을 덮어 식각함으로서 만들어진다. 새로운 WSW구조는 전계를 줄이기 위한 버퍼층으로 되어 있으며 WSW소자와 LDD구조의 소자 수명을 비교하였으며 핫-캐리어 열화 특성도 분석하였다. 또한 AC 핫-캐리어 열화를 칩 상에서 평가하기 위해 펄스 발생기, 레벨 시프터, 주파수 분배기를 포함한 테스트 패턴 회로를 설계하였다. 이러한 것은 AC와 DC 스트레스간의 핫-캐리어 열화 조건이 AC와 DC 스트레스 모두 동일한 물리적 메커니즘을 지닌다는 것을 알 수 있었다. 따라서 일반적으로 회로 동작 조건 하에서 DC 핫-캐리어 열화 특성을 토대로 AC 소자 수명도 예측할 수 있었다.

• 한국정밀공학회지
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• 제19권6호
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• pp.145-154
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• 2002

CMP (Chemical mechanical polishing) process was used to control the fine grinding process induced mechanical damage of Cz Silicon wafer. Characterization of mechanical damage was carried out using Nomarski microscope, magic mirror and also using angle lapping and lifetime scanner evaluation after heat treatment. Magic mirror and lifetime scanner were very useful for the residual damage pattern characterization and CMP process was effective on the reduction of fine grinding induced mechanical damage.

• 한국전기전자재료학회논문지
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• 제20권3호
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• pp.257-262
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• 2007

Organic light-emitting diodes (OLEDs) with the high efficieney and long lifetime are of growing interest in next-generation displays. Among the factors influencing OLEDs properties, one of unstable factor is $Alq_3$ cationic species caused by the excess holes resided in $Alq_3$ layer. Therefore, we suppressed the accumulation of excess holes by using the mixed-hole transporting layer (MHTL) of NPB and CBP in multilayer green OLEDs. The devices with MHTL showed improved characteristics in the luminous efficiency and lifetime. More characteristics and the carrier transport mechanism will be discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.67-68
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• 2006

Organic light-emitting devices (OLEDs) with the high efficiency and long lifetime are of growing interest in next-generation displays. Among the factors influencing OLEDs properties, one of unstable factor is $Alq_3$ cationic species caused by the excess holes resided in $Alq_3$ layer. Therefore, we suppressed the accumulation of excess holes by using the mixed-hole transporting layer (MHTL) of NPB and CBP in multilayer green OLEDs. The devices with MHTL showed improved characteristics in the luminance efficiency and lifetime. More characteristics and the carrier transport mechanism will be discussed.