• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• Journal of Power Electronics
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• v.16 no.2
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• pp.778-785
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• 2016

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.10a
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• pp.155-159
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• 1997

We investigated the effect of mechanical backside damage in Czochralski silicon wafer. The intensity of mechanical damage were evaluated by minority carrier recombination lifetime by a laser excitation/microwave reflection photoconductance decay method, photo-acoustic displacement method, X-ray section topography, and wet oxidation/preferential etch methods. The data indicate that the higher the mechanical damage intensity, the lower the minority carrier lifetime, and the photoacoustic displacement values are also increased proportionally.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.4
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• pp.408-413
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• 1995

We investigated the effect of mechanical backside damage upon minority carrier recombination lifetime measurement in Czochralski silicon substrate by laser excitation/microwave reflection photoconductance decay method. The intensity of mechanical damage was evaluated by X-ray double crystal rocking curve, X-ray section topography and wet oxidation/preferential etch methods. The data indicate that the higher the mechanical damage intensity, the lower the minority carrier lifetime, and the threshold full width at half maximum value which affect minority carrier lifetime measurement is about 13 secs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.311-317
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• 2008

The measurement of dark ${\sigma}_D$, gamma-induced ${\sigma}_{\gamma}$ conductivities and the expected conductivity modulation ${\Delta}_{\sigma}$ in silicon wafers/samples is studied for developing a new technique for carrier lifetime evaluation. In this paper a simple method is introduced to find the carrier lifetime variations with the measured conductivity and conductivity modulation under dark and gamma irradiation conditions. It will be concluded that this simple method enables us to give an improved wafer evaluation, processing and quality control in the field of photovoltaic materials and other electronic devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.27-34
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• 1999

We investigated the effect of mechanical back side damage in viewpoint of electrical and surface morphological characteristics in Czochralski silicon wafer. The intensity of mechanical damage was evaluated by minority carrier recombination lifetime by laser excitation/microwave reflection photoconductance decay technique, atomic force microscope, optical microscope, wet oxidation/preferential etching methods. The data indicate that the higher the mechanical damage degree, the lower the minority carrier lifetime, and surface roughness, damage depth and density of oxidation induced stacking fault increased proportionally.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.985-988
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• 2004

The carrier lifetime of boron doped Cz silicon samples after light induced degradation could be improved by optimized rapid thermal processing (RTP). The important five different parameters varied in order to investigate which parameter is important for the stable lifetime after light induced degradation, $\tau_d$. The Plateau temperature and the Plateau time influenced on the lifetime after light induced degradation. Especially, the Plateau temperature showed a strong influence on the stable lifetime. The optimal plateau temperature is approximately $900^{\circ}C$ t for a plateau time of 120 s. The stable lifetime increased from $15\mu}s$ to $25.5{\mu}s$. The normalized defect concentration, $N_t^*$, decreased from $0.06{\mu}s^{-1}$ to $0.037{\mu}s^{-1}$ by RTP-process.

• Korean Journal of Materials Research
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• v.25 no.9
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• pp.487-491
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• 2015

In photovoltaic power generation where minority carrier generation via light absorption is competing against minority carrier recombination, the substrate thickness and material quality are interdependent, and appropriate combination of the two variables is important in obtaining the maximum output power generation. Medici, a two-dimensional semiconductor device simulation tool, is used to investigate the interdependency in relation to the maximum power output in front-lit Si solar cells. Qualitatively, the results indicate that a high quality substrate must be thick and that a low quality substrate must be thin in order to achieve the maximum power generation in the respective materials. The dividing point is $70{\mu}m/5{\times}10^{-6}sec$. That is, for materials with a minority carrier recombination lifetime longer than $5{\times}10^{-6}sec$, the substrate must be thicker than $70{\mu}m$, while for materials with a lifetime shorter than $5{\times}10^{-6}sec$, the substrate must be thinner than $70{\mu}m$. In substrate fabrication, the thinner the wafer, the lower the cost of material, but the higher the cost of wafer fabrication. Thus, the optimum thickness/lifetime combinations are defined in this study along with the substrate cost considerations as part of the factors to be considered in material selection.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1264-1270
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• 2004

A fast switching thyristor with a superior trade-off property between the on-state voltage drop and the turn-off time could be fabricated by the proton irradiation method. After making symmetric thyristor dies with a voltage rating of 1,600 V from 350 $\mu$m thickness of 60 $\Omega$ㆍcm NTD-Si wafer and 200 $\mu$m width of n-base drift layer, the local carrier lifetime control by the proton irradiation was performed with help of the HI-13 tandem accelerator in China. The thyristor samples irradiated with 4.7 MeV proton beam showed a superior trade-off relationship of $V_{TM}$ = 1.55 V and $t_{q}$ = 15 $\mu$s attributed to a very narrow layer of short carrier lifetime(～1 $\mu$s) in the middle of its n-base drift region. To explain the small increase of $V_{TM}$ , we will introduce the effect of carrier compensation at the low carrier lifetime region by the diffusion current.ffusion current.t.