• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.387-400
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• 2017

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.420-423
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• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.103-104
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• 2012

In the AC module system, mismatch problem between AC power and constant input power is occurred. To solve this problem, electrolytic capacitor is utilized for diminishing power pulsation in PV side. However, it has disadvantages of low life span and weak in temperature. Decoupling method has been studied to reduce the capacitance and replaces electrolytic capacitor to film capacitor. This paper proposes design method for decoupling circuit which bidirectional DC-DC converter using soft switching. Proposed system is verified by design optimization and simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.35-41
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• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.347-353
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• 2017

We present a STT-MRAM read-circuit which mitigates the performance degradation caused by offsets from device mismatches. In the circuit, a single current source supplies read-current to both the data and the reference cells sequentially eliminating potential mismatches. Furthermore, an offset-free pre-amplification using a capacitor storing the mismatch information is employed to lessen the effect of the comparator offset. The proposed circuit was implemented using a 130-nm CMOS technology and Monte Carlo simulations of the circuit demonstrate its effectiveness in suppressing the effect of device mismatch.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.423-426
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• 2007

An active Balun is designed for RFID reader at 2.45GHz. The Balun is integrated inside the receiver, then the LNA and mixer can be connected. The unbalanced LNA output signal is transformed to a balanced signal at the input mixer The RF mixer and LO mixer, by using this balun. The Balun provided a balanced signal with two output stage, gain mismatch is 0.116dB. The phase show a good behavior with $163.918^{\circ}$,$-16.609^{\circ}$. The phase mismatch is about $0.527^{\circ}$. The tight difference between the gain and phase on each brancd, is because of the used capacitor and integrated inductor and the other parasitic element inside the balun.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.64-71
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• 2023

If an impedance mismatch occurs between the source and load in a Radio Frequency transmission system, reflected power is generated. This results in incomplete power transmission and the generation of Reflected Power, which returns to the Radio Frequency generator. To minimize this Reflected Power, Impedance matching is performed. Fast and efficient Impedance matching, along with converging reflected power towards zero, is advantageous for achieving desired plasma characteristics in semiconductor processes. This paper explores Impedance matching by adjusting the Vacuum Variable Capacitor of an L-type Matching Module based on the trends observed in the voltage of the Phase Sensor and Electromotive Force voltage. After assessing the impedance matching characteristics, the findings are described.