JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion

  • Lee, Youngjoo (Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH)) ;
  • Oh, Taehyoun (Department of Electronic Engineering, Kwangwoon University) ;
  • Park, In-Cheol (Department of Electrical Engineering, Korea Advanced Institute of Science and Technology)
  • Received : 2016.08.25
  • Accepted : 2017.03.27
  • Published : 2017.06.30
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Abstract

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

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References

  1. J.-I. Kim, D.-R. Oh, D.-S. Jo. B.-R.-S. Sung, and S.-T. Ryu, "A 65nm CMOS 7b 2 GS/s 20.7 mW flash ADC with cascaded latch interpolation," IEEE J. Solid-State Circuits, Vol. 50, No. 10, pp. 2319-2330, Oct. 2015. https://doi.org/10.1109/JSSC.2015.2460371
  2. H.-Y. Lee, D.-G. Jeong, Y.-J. Hwang, H.-B. Lee, and Y.-C. Jang, "A 1-V 1.6-GS/s 5.58-ENOB CMOS flash ADC using time-domain comparator," J. Semicond. Technol. Sci., Vol. 15, No. 6, pp. 695-702, Dec. 2015. https://doi.org/10.5573/JSTS.2015.15.6.695
  3. J. Yuan, S. W. Fung, K. Y. Chan, and R. Xu, "A 12-bit 20 MS/s 56.3 mW pipelined ADC with interpolation-based nonlinear calibration," IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 59, No. 3, pp. 555-565, Mar. 2012. https://doi.org/10.1109/TCSI.2011.2167272
  4. J.-S. Park, et al., "A 12b 100 MS/s three-step hybrid pipelined ADC based on time-interleaved SAR ADCs," J. Semicond. Technol. Sci., Vol. 14, No. 2, pp. 189-197, Apr. 2014. https://doi.org/10.5573/JSTS.2014.14.2.189
  5. J. L. McCreary and P. R. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques," IEEE J. Solid-State Circuits, vol. SC-10, no. 12, pp. 371-379, Dec. 1975.
  6. J. Craninckx and G. V. D. Plas, "A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007, pp. 246-247.
  7. B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007. https://doi.org/10.1109/JSSC.2007.892169
  8. B. P. Ginsburg and A. P. Chandrakasan, "An Energy-Efficient Charge Recycling Approach for a SAR converter With Capacitive DAC," in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 184-187.
  9. W. Y. Pang et al., "A 10-bi 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Application," in IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, 2009, pp. 149-152.
  10. C. C. Liu et al., "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process", in Proc. IEEE Symp. VLSI Circuits, 2009, pp. 236-237.
  11. C. C. Liu et al., "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. https://doi.org/10.1109/JSSC.2010.2042254
  12. J. S. Lee and I. C. Park, "Capacitor Array Structure and Switch Control for Energy-Efficient SAR Analog-to-Digital Converters," in Proc. IEEE Int. Symp. Circuits Syst., 2008, pp. 236-239.
  13. W. Yu et al., "Two-step split-junction SAR ADC," Electron. Lett., vol. 46, no. 3, pp. 208-210, Feb. 2010. https://doi.org/10.1049/el.2010.2392
  14. K. Bacrania, "A 12-bit Successive-Approximation-Type ADC with Digital Error Correction," IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1016-1025, Dec. 1986.
  15. W. Liu and Y. Chiu, "Background digital calibration of successive approximation ADC with adaptive equalisation," Electron. Lett., vol. 45, pp. 456-458, Apr. 2009. https://doi.org/10.1049/el.2009.2374
  16. F. Ohnhaeuser and M. Huemer, "Methods to eliminate dynamic errors in high-performance SAR A/D converter," in Proc. IEEE Int. Symp. Circuits Syst., 2008, pp. 2398-2401.
  17. V. Giannini et al., "An 820uW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2008, pp. 238-239.
  18. M. Hesener et al., "A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13 CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007, pp. 248-249.
  19. F. Kuttner, "A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13um CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 176-177.
  20. T. Ogawa et al., "SAR ADC algorithm with redundancy," in Proc. IEEE Asia Pacific Conf. Circuits Syst., 2008, pp. 268-271.
  21. Y. Lee and I.-C. Park, "Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters," in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 1464-1467.
  22. A. Johns and Ken Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, Inc., 1997.
  23. Y. Lee, J. Song, and I.-C. Park, "Statistical modeling of capacitor mismatch effects for successive approximation register ADCs," in Proc. IEEE Int. SoC Design Conf., 2011, pp. 302-305.