• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• 한국세라믹학회지
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• 제32권3호
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• pp.371-377
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• 1995

Silicon oxide films were grown on single-crystal silicon substrates at low temperatures (25~205$^{\circ}C$) in a low pressure electron cyclotron resonance (ECR) oxygen plasma. The growth rate of the silicon oxide film increased as the temperature increased or the pressure decreased. Also, the thickness of the silicon oxide film increased at negative bias voltage, but not changed at positive bias voltage. The growth law of the silicon oxide film was approximated to the parabolic form. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were studied using Al/SiO2/p-Si MOS structures. For a 10.2 nm thick silicon oxide film, the leakage current density at the electric field of 1 MVcm-1 was less than 1.0$\times$10-8Acm-2 and the breakdown field was higher than 10 MVcm-1. The flat band voltage of Al/SiO2/p-Si MOS capacitor was varied in the range of -2~-3 V and the effective dielectric constant was 3.85. These results indicate that high quality oxide films with properties that are similar to those of thermal oxide film can be fastly grown at low temperature using the ECR oxygen plasma.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.183-184
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• 2005

In this study, our varistors based on M.Matsuoke's composition were fabricated with ZnO nano-powder whose sizes were 50nm and 100nm. Electrical properties of ZnO nano-powder varistors were obtained by capacitance-voltage and frequency-real impedance. nano-powder varistors are indicated the change of the interface defects density $N_t$ at the grain boundaries and the donor concentration $N_d$ in the ZnO grains. Frequency analysis was accomplished to understand the equivalent circuit.

• Transactions on Electrical and Electronic Materials
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• 제17권4호
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 추계학술대회 논문집 전기물성,응용부문
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• pp.174-177
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• 2001

The voltage holding ratio (VHR) and Residual DC property in the in-plane switching (IPS) cell was studied Several IPS cells which have different concentrations of cynao liquid crystals (LCs) and different resistivities of fluorine LCs were fabricated VHR and residual DC voltage in the IPS cells using the capacitance-voltage (C-V) hysteresis method was measured. We found that the VHR of the IPS cell was decreasing with increasing concentration of cyano LC. The residual DC voltage of the IPS cell was decreasing with increasing concentration of cyano LCs. We suggest that the high polarity of cyano LC helps reducing the residual DC voltage.

• 한국전기전자재료학회논문지
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• 제21권12호
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• pp.1090-1095
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• 2008

The SiOCH films that low dielectric interlayer dielectric materials were deposited on p-type Si(100) substrates through the dissociation of BTMSM precursors with oxygen gas by using PECVD method. BTMSM precursor was introduced with the flow rates from 42 sccm to 60 sccm by 2 sccm step in the constant flow rate of 60 sccm $O_2$. SiOCH thin films were annealed at $450^{\circ}C$ for 30 minutes. The electrical property of SiOCH thin films was studied by MIS, Al/SiOCH/p-Si(100), structure. Annealed samples showed even greater reductions of the maximum capacitance and the dielectric constant of the SiOCH samples, owing to reductions of surface charge density. we confirmed this result with derivative of C-V characteristic, leakage current density. The maximum capacitance and leakage current density were respectively decreased about 4 pF, 60% after annealing. The average of low-k value is approximatly 2.07 after annealing.

• 유기물자원화
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• 제30권2호
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• pp.5-15
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• 2022

본 연구에서는 궐련형 담배의 담뱃잎 바이오매스 폐기물을 수거하여 슈퍼커패시터용 활물질로 제조 및 응용하였다. 수거한 담뱃잎 폐기물을 질소 환경에서 다양한 온도(800/850/950℃)로 탄화하였으며, 탄소/산소 성분비(C/O ratio) 분석을 통해 850℃에서 가장 우수한 품질의 탄소 물질이 제조되었음을 확인하였다. 추가적으로 담뱃잎 기반의 탄소 물질에 폴리피롤(Polypyrrole)을 저온중합법을 통해 코팅하여 전기화학적 성능을 향상시켰다. 탄소 물질(CTL-850)과 폴리피롤을 코팅한 탄소 물질(CTL-850/PPy)을 기반으로 한 전극의 전기화학적 성능을 측정한 결과, -1.0-0.0V와 0.0-1.0V의 전위창에서 각각 100.2F g^-1@1 A g^-1과 155.3F g^-1@1 A g^-1의 우수한 비정전용량(Specific capacitance)를 나타내었다. 두 개의 전극을 활용하여 비대칭형 슈퍼커패시터 소자(Asymmetric supercapacitor device)를 제작하였으며, 제조한 비대칭형 CTL-850//CTL-850/PPy 소자는 2.0V의 구동전압 범위와 비정전용량(31.1F g^-1@1 A g^-1)을 가지고 있음을 확인하였다. 또한, 제조한 슈퍼커패시터 소자의 방전을 통해 1.8V의 Red Led를 점등할 수 있음을 확인하였다. 본 연구 결과를 통해 바이오매스를 우수한 성능의 친환경 에너지 저장매체로 활용하는 후속 연구에 대한 방향성을 제시할 수 있을 것으로 판단된다.

• 전기전자학회논문지
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• 제18권4호
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• pp.620-624
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• 2014

본 연구에서는, Ni/CNT/$SiO_2$ 구조의 4H-SiC MIS 캐패시터를 제작하고 전기적 특성을 조사하였다. 이를 통하여 4H-SiC MIS 소자에서 탄소나노튜브의 역할을 분석하고자 하였다. 탄소나노튜브는 이소프로필알코올과 혼합하여 $SiO_2$ 표면에 분산하였다. 소자의 전기적 특성 분석을 위하여 300-500K의 온도 범위에서 소자의 정전용량-전압 특성을 측정하였다. 밴드 평탄화 전압은 양의 방향으로 shift되었다. 정전용량-전압 그래프로부터 계면 포획 전하 밀도 및 산화막 포획 전하 밀도가 유도되었다. 산화막의 상태는 4H-SiC MIS 구조의 계면에서 전하 반송자 또는 결함 상태와 관련된다. 온도가 증가함에 따라 밴드 평탄화 전압은 음의 방향으로 shift되는 결과를 얻었다. 실험 결과로부터, Ni과 $SiO_2$ 계면에 탄소나노튜브를 첨가함에 따라 4H-SiC MIS 캐패시터의 게이트 특성을 조절 가능할 것으로 판단된다.

• 반도체디스플레이기술학회지
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• 제16권1호
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• pp.70-74
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• 2017

To research the electrical properties of ZnS thin films with various annealing conditions, ZnS was prepared by RF magnetron sputtering system and annealed in a vacuum for 10 minutes. All films were analyzed by the XRD, PL and I-V measurement system. The XRD pattern of ZnS film annealed at $100^{\circ}C$ was shifted to lower 2 theta because of the formation of a depletion region at the interface between a substrate and ZnS thin film, and the capacitance was abruptly increased. However, the pattern of XRD of ZnS film annealed at $100^{\circ}C$ with a Schottky contact was showed the amorphous structure, and the current-voltage characteristics were non-linearly observed by the Schottky contact.

• 한국정보통신학회논문지
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• 제13권1호
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• pp.110-114
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• 2009

최근에 유기물 전계효과 트랜지스터의 연구는 전자소자분야에서 널리 알려져 있다. 특히 본 연구에서는CuPc 물질을 기본으로 하여 소자를 제작하고, 또한 기판의 온도를 달리 하여 제작하였다. CuPc FET 소자는 top-contact 방식으로 제작하였으며, 기판의 온도는 상온과 $150^{\circ}C$로 달리 하였다. 또한 CuPc의 두께는 40nm로 하였고, 채널의 길이는 $50{\mu}m$, 폭은 3mm로 하였다. 제작된 소자를 이용하여 전압-전류 특성을 측정하였다.