• IEIE Transactions on Smart Processing and Computing
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• 제3권4호
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• pp.246-250
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• 2014

Large mutual capacitance touch screen panels (TSP) are susceptible to display and ambient noise. This paper presents a multi-touch detection algorithm using an efficient noise compensation technique for large mutual capacitance TSPs. The sources of noise are presented and analyzed. The algorithm includes the steps to overcome each source of noise. The algorithm begins with a calibration technique to overcome the TSP mutual capacitance variation. The algorithm also overcomes the shadow effect of a hand close to TSP and mutual capacitance variation by dynamic threshold calculations. Time and space filters are also used to filter out ambient noise. The experimental results were used to determine the system parameters to achieve the best performance.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.128.2-128
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• 2001

Since pulse energization can improve the performance of Electrostatic Precipitator(ESP) for high resistivity dusts, high voltage micro-pulse generators, 70kV 140usec duration pulses for instance, are commonly developed by LC resonance for most pulse powered ESPs. Consisting of discharge electrodes and collecting electrodes, ESP has its own capacitance like a capacitor. ESP's capacitance affects the LC resonance phenomenon with resonance inductor and capacitor of micro-pulse power supply, engineers should acquire the value of their ESP to design for proper power supply design. In this study, we describe the ESP's capacitance measuring device which has the same topology with our new developed micro-pulse power supply. In this microcontroller based capacitance measuring equipment, ESP's capacitance can be calculated easily through ...

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.968-969
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• 2015

This paper proposes a novel analysis method for calculating inverter DC bus capacitance and line reactor parameters. In the realization process, DC bus capacitance parameter, and ripple current, life of DC bus capacitor, interaction between DC bus capacitance can be calculated by using Newton-Raphson procedure. The design scheme of DC bus capacitor and line reactor, specific parameters such as capacitance, loss, ripple current, central average temperature, life, ripple current, loss, size, central temperature of the reactor were given. Simulation results show that this scheme can accurately calculate the DC bus capacitance and line reactor parameters. Compared with calculation result of references, cost and volume are half. The indicators meet the demand of practical engineering. It had affirmed precision of the analytical method and verified correctness and feasibility of this method.

• 한국세라믹학회지
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• 제46권2호
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• pp.161-169
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• 2009

MLCC (Multi-layer Ceramic Capacitor) is the most important passive component in electronic devices such as HHP, PC and digital display. The development trend of MLCC is a miniaturization with increasing the capacitance. In this paper, a development history of the high capacitance MLCC in Korea was introduced, and the necessity of the finer $BaTiO_3$ was explained in the viewpoint of the issued electrical and dielectric properties of high capacitance MLCC. The bottleneck technologies to realize the high capacitance was shortly introduced, followed by the prediction of the development trend of MLCC in near future.

• 대한안전경영과학회:학술대회논문집
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• 대한안전경영과학회 2003년도 추계학술대회
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• pp.343-350
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• 2003

The best Ppy weight ratio was 7 wt% and the optimal electrode composition ratio was 78 : 17 : 5 wt.% of (MSP-20 : BP-20 =1 : 1), (Super P : Ppy =10 : 7) and P(VdF-co-HFP). Implantation of Ppy as the conducting agents have led to superior electrochemical characteristics because of the low of internal resistance and faradaic capacitance. The result of unit cell with Ppy 7 wt% were as follows: 28.02 Fig of specific capacitance, 1.34 Ω of DC-ESR and 0.36 Ω of AC-ESR. Unit cell showed a good stability up to 200 charge-discharge cycles, retaining 82% of their original capacity at 200 cycles. From the analysis of impedance, the electrodes with Ppy 7 wt% showed low ESR, low charge transfer resistance and quick reaction rate. It was inferred that quick charge-discharge was possible. As compared with the specific capacitance (rectangular shape) of CV, it was also concluded that the specific capacitance originated from thecompound phenomena of the faradaic capacitance by oxidation and reduction of Ppy and the non-faradaic capacitance by adsorption-desorption of activated carbon.

• 한국생산제조학회지
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• 제25권4호
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• pp.307-311
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• 2016

Several types of supercapacitors have been developed for energy storage systems. Among them, the hybrid type has advantages such as a large capacitance per weight compared with the electric double-layer capacitator type. In this study, constant current charging and discharging tests were conducted for recently developed hybrid-type supercapacitors. Based on the experimental results, the capacitance and equivalent series resistance were obtained. The capacitance was larger than the designed capacitance at a low current but became small at a high current. In addition, the capacitance depended on the cell voltage. These results can be used to design an energy storage system.

• 태양에너지
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• 제2권1호
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• pp.17-23
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• 1982

This paper presents the performance of a Flat-Plate Solar Collector in case of taking into account of the thermal capacitance. The relationships among energy absorption, overall heat loss coefficient and temperature distribution are studied theoretically. And the thermal capacitance of the collector is considered. Also, the results obtained are compared with those of model in which the thermal capacitance is neglected. As the results of this study, the efficiency of the collector having double glazing is higher than the other cases. It is shown that the fluid temperature in the tubes are rising close to linearly. The variations of the outlet temperature of tubes in the model neglecting the effect of thermal capacitance are tend to represent lower slope than that of considering the effect of thermal capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• Journal of information and communication convergence engineering
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• 제19권4호
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• pp.263-268
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• 2021

Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.