• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of Korean Clinical Health Science
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• v.5 no.1
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• pp.816-824
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• 2017

Purpose. This study was classified into normal and demented elderly through K-MMSE. The purpose of this study was to analyze gait characteristics of normal elderly and demented peoples using GAITRite walking system. Methods. The subjects of this study were selected as elderly people receiving home visit physical therapy. An independent t-test was conducted to verify the statistical significance of the time-space variables of the elderly with dementia. Results. Step time(p=0.041), cycle time(p=0.037), distance(p=0.024), and cadence(p=0.048) were significantly shorter in the normal elderly than in the demented elderly on flat place. The mean age was significantly longer in normal elderly than in elderly persons with dementia. Step time(p=0.022), cycle time(p=0.023), distance(p=0.019), and cadence(p=0.015) were significantly shorter in the mat walking. The mean age was significantly longer in normal elderly than in elderly patients with dementia. Stretch time, cycle time, distance, and hair support time were significantly shorter in the mat walking. The mean age of the elderly was significantly longer than that of the elderly with dementia. The spinal support time, which is a spatial variable, was significantly shorter in the normal elderly than in the demented elderly. Conclusions. It compares the various gait characteristics of the normal and demented elderly people, thereby increasing the walking ability of the elderly person more effectively. This study should be utilized as basic data for preventing fall-down.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4984-4990
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• 2010

In this paper, a Step-down CMOS DC-DC Converter using low power switched capacitor method is designed in a 0.5 ${\mu}m$ technology for the integration of devices. Conventional DC-DC converter is used inductor that can store energy in a magnetic field but have low efficiency because power consumption is caused by magnetic flux. And there were problems with size, weight and price to integrate chip. In this paper, a proposed Inductorless step-down CMOS DC-DC converter of low power using SC method is designed in a 0.5um technology to solve these problems. Designed DC-DC converter have 96% power efficiency with 200kHz frequency by using cadence simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

• Journal of the Korean Society of Physical Medicine
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• v.13 no.3
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• pp.19-25
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• 2018

PURPOSE: Most gait assessment tools are expensive and require controlled laboratory environments. Tri-axial accelerometers have been used in gait analysis as an alternative to laboratory assessments. Many smartphones have added an accelerometer, making it possible to assess spatio-temporal gait parameters. This study was conducted to confirm the reliability and validity of a smartphone-based accelerometer at quantifying spatio-temporal gait parameters of stroke patients when attached to the body. METHODS: We measured gait parameters using a smartphone accelerometer and gait parameters through the GAITRite analysis system and the reliability and validity of the smartphone-based accelerometer for quantifying spatio-temporal gait parameters for stroke patients were then evaluated. Thirty stroke patients were asked to walk at self-selected comfortable speeds over a 10 m walkway, during which time gait velocity, cadence and step length were computed from smartphone-based accelerometers and validated with a GAITRite analysis system. RESULTS: Smartphone data was found to have excellent reliability ($ICC2,1{\geq}.98$) for measuring the tested parameters, with a high correlation being observed between smartphone-based gait parameters and GAITRite analysis system-based gait parameters (r = .99, .97, .41 for gait velocity, cadence, step length, respectively). CONCLUSION: The results suggest that specific opportunities exist for smartphone-based gait assessment as an alternative to conventional gait assessment. Moreover, smartphone-based gait assessment can provide objective information about changes in the spatio-temporal gait parameters of stroke subjects.

• Journal of Korean Physical Therapy Science
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• v.10 no.2
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• pp.17-28
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• 2003

The aim of this study was to investigate the effects of treadmill gait training on the functional characteristics and the temporal-distance parameters of gait in hemiplegic patients, as compared with conventional gait training. The subjects of this study were 32 hemiplegic patients who had been admitted or were visited out-patients at Kangdong Sacred Heart Hospital, Hallym University, from March 3 through April 25, 2003. These subjects were randomly divided into treadmill gait training group or conventional gait training group. We evaluated the gait ability, motor functions, muscle strength, spasticity, physiological cost index, and temporal-distance parameters. We analyzed the changes between pre and post training in each groups, and the difference between two groups. Temporal-distance parameters were obtained using the ink footprint method and then energy consumption using physiological cost index. The results were as follows: 1. After a six-week training, treadmill gait training group significantly improved, as. compared to pre-training, in gait ability, motor functions for the leg and trunk and gross function, muscle strength of the lower limb, gait speed, cadence, step length both on the affected and on the unaffected side, step length symmetry, and energy consumption(p<0.05). 2. After a six-week training, conventional gait training group significantly improved, as compared to pretraining, in gait ability, motor functions for the leg and trunk, muscle strength of the lower limb, spasticity the upper limb, gait speed, cadence, step length both on the affected and on the unaffected side, and energy consumption(p<0.05). 3. After a six-week training, the treadmill gait training group significantly improved, as compared to the conventional gait, training, in gait speed and step length on the unaffected side. These results show that treadmill gait training was improved gait speed and step length on the unaffected side of hemiplegic patients, as compared with conventional gait training. Further research is needed to confirm the generalization of these findings and to identify which hemiplegic patients might benefit from treadmill gait training.

• Physical Therapy Rehabilitation Science
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• v.4 no.2
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• pp.94-102
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• 2015

Objective: The purpose of this study is to investigate the effect of treadmill gait training with patellar taping on gait abilities in chronic stroke patients. Design: Randomized controlled trial. Methods: Thirty chronic stroke patients who have been diagnosed at least six months or before were recruited in Gyeongin Rehabilitation Center Hospital, located in Incheon. Patients who were enrolled in this study were randomized to experimental group (n=15) or control group (n=15). Treadmill with patella taping training group patients were applied with patellar taping when they were being trained on a treadmill. Control group patients were being trained on a treadmill without any kind of taping. Gait parameters were measured with a GAITRite$^{(R)}$ system which evaluated gait performances. Gait trainings were done for 30 min/day, 5 days/week, for 4 weeks. Results: After treadmill training, treadmill with patella taping training group showed a significant improvement in gait abilities, including velocity, cadence, paretic and non-paretic step length, and double support period (p<0.05). However, in general treadmill group, there were no significant differences in gait parameters except velocity and cadence. There was a significant difference in gait performance in the experimental group compared with the control group, except for the gait symmetry ratio (p<0.05). Conclusions: According to this result of this study, it seems that application of patellar taping in treadmill gait training for chronic stroke patients significantly improved gait abilities of these patients. Also, we can conclude that patella taping is thought to be useful in real clinical settings where there are many chronic patients who are in need of improvement in their gait abilities.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.26-36
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• 1999

In this paper, the novel scheme of OAM performance management function is proposed to supply the most of network resources and reliable services by processing data having various QoS(quality of service) in the view of cell loss and cell delay of ATM networks Also, the special fields of OAM cell are defined in order to improve correlate control, operation, and management technique between networks which is required to flexibility and precision control as detecting the performance information of the variable networks periodically. The proposed OAM function, the input/output function of cell, and the interface function of the accessory device which is likely to the memory/CPU are designed to ASIC. The designed chip is carried out the back-end simulation using Verilog-XL simulator of Cadence. In result, it is able to performs an accurate control in $2{\mu}s$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.50-56
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• 2016

This paper proposes the architecture and design of intra prediction circuit for a multi-decoder supporting UHD images. The proposed circuit supports not only the latest video compression standard HEVC but also H.264. In addition to the basic function of performing intra prediction, this circuit has the capability of performing the reference sample filter operation defined in the H.264 standard, and the smoothing and strong sample filter operations defined in the HEVC standard. We reduced the circuit size by sharing the circuit blocks for common operations and internal storage, and improved the circuit performance by parallel processing. The proposed circuit was described at RTL using Verilog HDL and its functionality was verified by using NC-Verilog of Cadence. The RTL circuit was synthesized by using Design Compiler of Synopsys and 130nm standard cell library. The synthesized gate-level circuit consists of 69,694 gates and processes 100 ~ 280 frames per second for 4K-UHD HEVC images at the maximum operation frequency of 157MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.27-35
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• 1999

In a typical spread spectrum system, parallel correlator occupies a large fraction of power consumption because of the large number of accumulators in the system. In this paper, a novel accumulator is proposed that can reduce the power consumption in the parallel correlator. The proposed accumulator counts the numbers of 1 of the incoming input data. The counted values are weighted and added together to obtain the final correlation value only at the end of the accumulation. The proposed accumulator has been designed and simulated by CADENCE Verilog-XL and synthesized by SYNOPSYS Design Compiler with $0.6{\mu}m$ standard cell library. Power consumption results have been obtained from EPIC PowerMill simulations. Simulation results are very encouraging. First, the power dissipation is reduced by 22% and the maximum operating frequency is increased by 323%. In addition, the parallel correlator using the proposed accumulators consumed less power than the conventional active parallel correlators by 22%, and less power than the conventional passive correlator by 43%.