• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.15 no.11
• /
• pp.3892-3912
• /
• 2021

The recent rapid growth of mobile network traffic places multi-access edge computing in an important position to reduce network load and improve network capacity and service quality. Contrasting with traditional mobile cloud computing, multi-access edge computing includes a base station cooperative cache layer and user cooperative cache layer. Selecting the most appropriate cache content according to actual needs and determining the most appropriate location to optimize the cache performance have emerged as serious issues in multi-access edge computing that must be solved urgently. For this reason, a cache placement algorithm based on comprehensive utility in big data multi-access edge computing (CPBCU) is proposed in this work. Firstly, the cache value generated by cache placement is calculated using the cache capacity, data popularity, and node replacement rate. Secondly, the cache placement problem is then modeled according to the cache value, data object acquisition, and replacement cost. The cache placement model is then transformed into a combinatorial optimization problem and the cache objects are placed on the appropriate data nodes using tabu search algorithm. Finally, to verify the feasibility and effectiveness of the algorithm, a multi-access edge computing experimental environment is built. Experimental results show that CPBCU provides a significant improvement in cache service rate, data response time, and replacement number compared with other cache placement algorithms.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.11_12
• /
• pp.608-616
• /
• 2005

A cache architecture is proposed here which evokes prefetch at level 1 cache miss. Existing structures only prefetch at level 2 cache miss. In the proposed cache architecture, level 1 cache miss would select demand fetch block and prefetch block from the level 2 cache and store to level 1 cache and prefetch cache, respectively. According to an experimental analysis using 11 benchmark programs, the hierarchical cache architecture that employs both a level 1 cache prefetcher and a level 2 cache prefetcher obtained a maximum $19\%$ increased performance when compared to the cache architecture that employs only a level 2 cache prefetcher.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.3
• /
• pp.802-810
• /
• 1997

In this paper, the performance of direce mapping caches, 2_, 4_, 8_, .., 4096_way way set associative caches, and fully assiciative caches are analyized by trace simulation for verivying their effectiveness.In general, it is well known that as n, the number of main memory lines to be stored into one cache line number in direct mapping cache, increases, the performance of the cache memory should get higher linearly.According to our analysis, however, it is not true on all the cache organizations.It is shown that as n increases, miss ratios get lower only when the small cache(less than 256K) using large line size is used.It is also shown that fully associative mapping achieves high performance only when small size cache using large line size ia used.

• Journal of the Korea Society for Simulation
• /
• v.12 no.2
• /
• pp.35-44
• /
• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• Journal of Communications and Networks
• /
• v.9 no.1
• /
• pp.43-49
• /
• 2007

The implementation of client polling as a weak cache coherence mechanism has two major drawbacks: Firstly, the cache may return a stale copy if the object is changed in the origin server while the cached copy is considered valid. Secondly, the cache can invalidate a cached copy that is still valid in the server. Therefore, we propose a multilevel pre-fetching (MLP) in conjunction with the client polling to refine these drawbacks. MLP is introduced to improve the level of freshness among the cached objects. The simulation results presented in this paper show that the proposed MLP significantly minimizes the number of stale objects and reduces the invalidation messages sent out to the server, i.e., increase the cache HIT rate.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.7 no.7
• /
• pp.1610-1623
• /
• 2013

In-network caching is a key component of information-centric networking (ICN) for reducing content download time, network traffic, and server workload. Data center network (DCN) is an ideal candidate for applying the ICN design principles. In this paper, we have evaluated the effectiveness of caching placement and replacement in DCN with butterfly-topology. We also suggest a new cache placement policy based on the number of routing nodes (i.e., hop counts) through which travels the content. With a probability inversely proportional to the hop counts, the caching placement policy makes each routing node to cache content chunks. Simulation results lead us to conclude (i) cache placement policy is more effective for cache performance than cache replacement, (ii) the suggested cache placement policy has better caching performance for butterfly-type DCNs than the traditional caching placement policies such as ALWASYS and FIX(P), and (iii) high cache hit ratio does not always imply low average hop counts.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.6 s.38
• /
• pp.153-166
• /
• 2005

Existing single cache structure has shown difference of hit-ratio according to individually replacement strategy However. It needs new improved cache structure for reducing network traffic and providing advanced hit-ratio. Therefore, this Paper design push agent model using dual cache for increasing hit-ratio by reducing server overload and network traffic by repetition request of persistent and identical information. In this model proposes dual cache structure to do achievement replace gradual cache using by two caches storage space for reducing server overload and network traffic. Also, we show new cache replace techniques and algorithms which executes data update and delete based on replace strategy of Log(Size) +LRU, LFU and PLC for effectiveness of data search in cache. And through an experiment, it evaluates Performance of dual cache push agent model.

• Journal of KIISE
• /
• v.42 no.2
• /
• pp.177-182
• /
• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• Journal of Industrial Convergence
• /
• v.18 no.2
• /
• pp.69-75
• /
• 2020

Industrial IoT has much interested in wireless mesh networks (WMNs) due to cost effectiveness and coverage. According to the advance in caching technology, WMNs have been researched to overcome the throughput degradation of multihop environment. However, there is few researches of cache power consumption models for WMNs. In particular, a wired line based cache power consumption model in content-centric networks is not still proper to WMNs. In this paper, we split the amount of cache power from the idle power consumption of CPU, and then the cache hit ratio proportional power consumption model (CHR-model) is proposed. The proposed CHR-model provides more accurate power consumption in WMNs, compared with the conventional cache power efficiency based consumption model (CPE-model). The proposed CHR-model can provide a reference model to improve energy-efficient cache operation for Industrial IoT.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.52-58
• /
• 2013

Replacement policy is one of the key factors determining the effectiveness of a cache. The LRU replacement policy has remained the standard for caches for many years. However, the traditional LRU has ineffective performance in zero-reuse line intensive workloads, although it performs well in high temporal locality workloads. To address this problem, We propose a new replacement policy; DCR(Dynamic Counter based Replacement) policy. A temporal locality of workload dynamically changes across time and DCR policy is based on the detection of these changing. DCR policy improves cache miss rate over a traditional LRU policy, by as much as 2.7% at maximum and 0.47% at average.