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A Cache Controller to Maximize Effectiveness of Hierarchical Memory Architecture  

Uh Bong Yong (유비쿼터스 바이오정보기술센터)
Ju Young Kwan (충북대학교 컴퓨터과학과)
Cheon Joong Nam (충북대학교 전기전자컴퓨터공학부)
Kim Suk Il (충북대학교 전기전자컴퓨터공학부)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.32, no.11_12, 2005 , pp. 608-616 More about this Journal
Abstract
A cache architecture is proposed here which evokes prefetch at level 1 cache miss. Existing structures only prefetch at level 2 cache miss. In the proposed cache architecture, level 1 cache miss would select demand fetch block and prefetch block from the level 2 cache and store to level 1 cache and prefetch cache, respectively. According to an experimental analysis using 11 benchmark programs, the hierarchical cache architecture that employs both a level 1 cache prefetcher and a level 2 cache prefetcher obtained a maximum $19\%$ increased performance when compared to the cache architecture that employs only a level 2 cache prefetcher.
Keywords
Prefetch Cache; Memory Hierarchy Architecture; Simulation;
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Times Cited By KSCI : 2  (Citation Analysis)
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