• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.50-69
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• 2001

Three kinds of high-speed signaling methods for synchronous DRAM (SDRAM) bus interface channels (PC-133, Direct-Rambus, and SSTL-2) were analyzed in terms of the timing budget and the physical transmission characteristics. To analyze the SDRAM bus interface channels, loss mechanisms and the effective characteristic impedance method were reviewed and the ABCD matrix method was proposed as an analytic and yet accurate method. SPICE simulations were done to get the AC responses and the eye patterns of the three SDRAM bus interface channels for performance comparisons. Recent progress and future trend for SDRAM bus interface standards were reviewed.

• 한국정보통신학회논문지
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• 제10권6호
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• pp.1045-1054
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• 2006

본 논문에서는 MIL-STD-1553 data bus 네트워크의 다중화를 위한 버스 인터페이스 모듈의 설계에 관하여 기술하였다. 일반적으로 MIL-STD-1553 네트워크는 단일 레벨의 버스 토플로지를 사용하지만 응용 시스템의 구조에 따라 데이터 버스의 다중화가 요구된다. 버스의 다중화를 위해서는 마이크로 프로세서가 사용되며, 시스템의 하드웨어와 소프트웨어의 추가 기능이 요구된다. 설계된 인터페이스 모듈은 마이크로 프로세서의 사용 없이 통신용 트랜시버와 간단한 전자회로로 구성되어 있다. 하드웨어 테스트 및 소프트웨어 시뮬레이션 통하여 설계 제작된 모듈의 성능을 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• 해양환경안전학회지
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• 제20권3호
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• pp.318-322
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• 2014

A kind of field bus called Actuator and Sensor interface bus(AS-i) was designed in this paper. The configuration of AS-i network system used Application Specific Integrated Circuit(ASIC) SAP5S chip and PLC S7-200 station, which included CPU 224 and AS-i master module CP 243-2. We also created an example program for PLC S7-200 to control AS-i network. The fire and smoke detection system was made with AS-i network system that was designed. This system had got more advantages than other system such as number of stations, easy installation, wide working area, etc. And designed system can be used as a partner network for higher level field bus networks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 심포지엄 논문집 정보 및 제어부문
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• pp.193-194
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• 2008

This paper defines the electrical interfaces and limited items to integrate Ka-band communication payload on the satellite system, which includes the detailed interfaces such as bus voltage and data bus according to the related COMS requirements. And the BUS Electrical Interface Simulator introduces to use during the course of validating and accepting between the KA-Band payload and their EGSE. These interface design results are fully validated through the testing with the BEIS and is compliant with the satellite interface control interface requirements.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1836-1839
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• 2005

We have developed Ethernet based real-time communication systems called "Vnet/IP" for DCS which is the control system for process automation. This paper describes the features and the technologies of the ASIC which is utilized in the communication interface hardware for Vnet/IP. Vnet/IP has been developed for mission-critical communications. Hence it has real-time feature, high reliability and precise time synchronization capability. At the same time, it is able to deal with standard protocols without influence on mission-critical communications. The communication interface hardware has a host interface and dual redundant network interfaces. The host interface can be chosen PCI-bus or R-bus which is the proprietary internal bus developed for the high reliable redundant controller. Each network interface is a RJ45 connection with 1Gbps maximum in compliance with IEEE802.3.

• 전자공학회논문지C
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• 제35C권1호
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.

• 한국통신학회논문지
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• 제29권4A호
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• pp.390-398
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• 2004

본 논문은 SoC 설계시 AMBA 버스와 다른 프로토콜을 갖는 IP간의 통신을 위한 인터페이스 설계를 위한 확장 STG 표현을 제안하며, 이를 적용하여 다양한 IP간의 통신을 위한 프로토콜 탐색 알고리즘과 인터페이스를 자동 생성하는 시스템의 구축을 제시한다. 시스템은 동기/비동기 전송타입, 데이터 사이즈 등이 서로 다른 프로토콜을 갖는 IP 간의 데이터 전송이 가능한 인터페이스 모듈을 생성한다. AMBA AHB 버스와 타겟 IP로써 비디오 디코더간의 매뉴얼한 인터폐이스 설계와 자동생성된 모듈간의 성능을 비교한 결과 burst 통신의 성능은 거의 차이를 보이지 않았다. Single 통신의 경우 매뉴얼한 설계에 비해 다소 떨어지는 성능을 보여줬으나 전체 IP의 면적을 고려할 때 극히 미미한 면적 증가만을 보였다.