• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.12
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• pp.1005-1012
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• 2020

Avionics systems that use the PCI-Express bus unfortunately cannot use at least one I/O device if the bus fails, because the I/O device is connected to CPU through only one PCI-Express channel. This paper presents a fault-tolerant architecture of the PCI-Express bus for avionics systems, which tolerates one channel failure with help of the other redundant channel that has not been failed. In this architecture, each redundant PCI-Express channel connects a corresponding port of CPU to each switch logic of channels to provide each I/O device through a switched fault-tolerant channel. This paper includes the results of experimentation to show that the architecture detects the faulty condition in real time and switches the channel to the other redundant channel which has not been failed, when the architecture meets a failure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of Korea Society of Industrial Information Systems
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• v.27 no.6
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• pp.51-58
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• 2022

Microcontroller (MCU) is designed to properly utilize each module through programming by connecting various modules to Advanced Microcontroller Bus Architecture (AMBA). General-purpose MCUs are designed for consumers to use them appropriately in their research or industry area. However, in a specific area such as networking and AI autonomous vehicles, it is necessary to design MCU suitable for the field directly. However, there is a significant barrier for most consumers to directly design an MCU. In this paper, we provide a development guideline that can easily design an MCU for education or research purpose. First, we introduce AMBA system with open IPs, and we verify that the module operates properly through AMBA and interrupt operation. Finally, the MCU system is designed as an on-chip.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.29-42
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• 1994

The architecture of a MIMD-type parallel computer system is specified: a simulator is developed to support design and evaluation of systems based on the architecture: and conducted with the simulator to evaluate system performance. The horizontal/vertical-bus(H/V-bus) system architecture provides an NxN array of processing elements which communicate with each other through a network of N horizontal buses and N vertical buses. The simulator, written in SLAM II and FORTRAN, is designed to provide high-resolution in simulating the IPC mechanism. Parameters provide the user with independent control of system size, PE speed and IPC mechanism speed. Results generated by the simulator include execution times, PE utilizations, queue lengths, and other data. The simulator is used to study system performance when a partial differential equation is solved by parallel Gauss-Seidel method. For comparisons, the benchmark is also executed on a single-bus system simulator that is derived from the H/V-bus system simulator. The benchmark is also solved on a single PE to obtain data for computing speedups. An extensive analysis of results is presented.

• Journal of The Korea Institute of Healthcare Architecture
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• v.22 no.2
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• pp.7-14
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• 2016

Purpose: Caring for weak person in society, which increases the population of the elderly and people with disabilities is essential. By increasing along with the increase of the use of passenger facilities for travelers and pedestrian is increasing the demand for convenient and secure facilities for everyone. The emerging importance of the passenger-related facilities, but a representative study of the bus terminal facilities is lacking. Bus terminals are the most popular passenger facility. Thus, the bus terminal can be conveniently used by anyone in everyday life, however, the applied elements considering the use of the transportation Poor are not sufficient. Methods: This study was conducted to evaluate BF certification standards targeting bus terminals across the country to determine the availability of the transportation Poor in bus terminal. Result: As a result of the bus Terminal possibility BF certified it appeared to be very low. Also, items received the lowest rating of each item was evaluated in the informative facilities and items. Bus terminal is a facility used by the unspecified individuals, the proportion of first-time user is high, but there is a lack of consideration for the transportation Poor bus terminals. Implications: In the future, this study can guide the next research on the application of BF certification standards in bus terminal. Further studies can be presented to the improvement of the BF certification indicator in bus terminal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.33-39
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• 2011

H.264 decoders usually have pipeline architecture by a macroblock or a 4 ${\times}$ 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.