• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.21-28
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• 2004

We have demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon ) printed circuit board (PCB). The copper lines were formed with 100$\mu\textrm{m}$ width and 18$\mu\textrm{m}$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of 100-200$\mu\textrm{m}$. The DFRs of 15$\mu\textrm{m}$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100{\circ}C$ to 15$0^{\circ}C$ and laminating speed from 0.28-0.98cm/s. We have found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63cm/s. And the smallest size of indium solder bump was diameter of 50$\mu\textrm{m}$ with pitch of 100$\mu\textrm{m}$.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.169-173
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• 2003

We demonstrated the applicability of dry film photoresist (DFR) in photolithography process for fine pitch solder bumping on the polytetrafluoroethylene (PTFE/Teflon) printed circuit board (PCB). The copper lines were formed with $100\;{\mu}m$ width and $18\;{\mu}m$ thickness on the PTFE test board, and varying the gaps between two copper lines in a range of $100-200\;{\mu}m$. The DFRs of $15\;{\mu}m$ thickness were laminated by hot roll laminator, by varying laminating temperature from $100^{\circ}C\;to\;150^{\circ}C$ and laminating speed. We found the optimum process of DFR lamination on PTFE PCB and accomplished the formation of indium solder bumps. The optimum lamination condition was temperature of $150^{\circ}C$ and speed of about 0.63 cm/s. And the smallest size of indium solder bump was diameter of $50\;{\mu}m$ with pitch of $100\;{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.59-64
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• 2013

In-situ annealing tests of Cu/Ni/Au/Sn-Ag/Cu micro-bump for 3D IC package were performed in an scanning electron microscope chamber at $135-170^{\circ}C$ in order to investigate the growth kinetics of intermetallic compound (IMC). The IMC growth behaviors of both $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ follow linear relationship with the square root of the annealing time, which could be understood by the dominant diffusion mechanism. Two IMC phases with slightly different compositions, that is, $(Cu,Au^a)_6Sn_5$ and $(Cu,Au^b)_6Sn_5$ formed at Cu/solder interface after bonding and grew with increased annealing time. By the way, $Cu_3Sn$ and $(Cu,Au^b)_6Sn_5$ phases formed at the interfaces between $(Cu,Ni,Au)_6Sn_5$ and Ni/Sn, respectively, and both grew with increased annealing time. The activation energies for $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ IMC growths during annealing were 0.69 and 0.84 eV, respectively, where Ni layer seems to serve as diffusion barrier for extensive Cu-Sn IMC formation which is expected to contribute to the improvement of electrical reliability of micro-bump.

• Korean Journal of Metals and Materials
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• v.49 no.2
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• pp.180-186
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• 2011

Isothermal annealing and electromigration tests were performed at $125^{\circ}C$ and $125^{\circ}C$, $3.6{\times}10_4A/cm^2$ conditions, respectively, in order to compare the growth kinetics of the intermetallic compound (IMC) in the Cu/thin Sn/Cu bump. $Cu_6Sn_5$ and $Cu_3Sn$ formed at the Cu/thin Sn/Cu interfaces where most of the Sn phase transformed into the $Cu_6Sn_5$ phase. Only a few regions of Sn were not consumed and trapped between the transformed regions. The limited supply of Sn atoms and the continued proliferation of Cu atoms enhanced the formation of the $Cu_3Sn$ phase at the Cu pillar/$Cu_6Sn_5$ interface. The IMC thickness increased linearly with the square root of annealing time, and increased linearly with the current stressing time, which means that the current stressing accelerated the interfacial reaction. Abrupt changes in the IMC growth velocities at a specific testing time were closely related to the phase transition from $Cu_6Sn_5$ to $Cu_3Sn$ phases after complete consumption of the remaining Sn phase due to the limited amount of the Sn phase in the Cu/thin Sn/Cu bump, which implies that the relative thickness ratios of Cu and Sn significantly affect Cu-Sn IMC growth kinetics.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.9-16
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• 2005

This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.85-90
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• 2011

With regard to reliability of solder joint, the significant failures include open defects that occurs from alignment problem, Head in Pillow by PCB's warpage, the crack of solder by CTE mismatch, and the crack of IMC layer by mechanical impact. Especially as PCB down-sizing and surface finish is under progress, brittle failure of IMC layer between solder bump and PCB pad becomes a big issue. Therefore, it requires enhancing the level of difficulty in the existing assessment method and improving the measurement through the study on the mechanism of IMC formation, growth and brittle failure. Under this circumstance, this study is intended to suggest the direction of research for improving the reliability on the crack such as improvement of IMC brittle fracture.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.65-69
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• 2010

In this study, we investigated the effects of UBM(Under Bump Metallization) and solder composition on the drop impact reliability of wafer level packaging. Fan-in type WLP chips were prepared with different solder ball composition (Sn3.0Ag0.5Cu, and Sn1.0Ag0.5Cu) and UBM (Cu 10 ${\mu}m$, Cu 5 ${\mu}m$\Ni 3 ${\mu}m$). Drop test was performed up to 200 cycles with 1500G acceleration according to JESD22-B111. Cu\Ni UBM showed better drop performance than Cu UBM, which could be attributed to suppression of IMC formation by Ni diffusion barrier. SAC105 was slightly better than SAC305 in terms of MTTF. Drop failure occurred at board side for Cu UBM and chip side for Cu\Ni UBM, independent of solder composition. Corner and center chip position on the board were found to have the shortest drop lifetime due to stress waves generated from impact.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.122-127
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• 2003

본 논문에서는 새로운 솔더 범프 형성 방법 중의 하나인 Solder droplet jetting에 의한 솔더 범프 형성 공정에 대해 연구하였으며, 이를 위해 솔더 제팅 직후의 안정한 솔더 액적(solder droplets)의 형성을 위한 공정 변수들의 영향에 대해 먼저 알아보았다 이를 위해 제팅 노즐에 가해지는 파형과 용융 솔더의 온도, 질소 가스의 압력 등에 의한 영향을 주로 살펴보았다. 다음으로 리플로를 거쳐 솔더 범프를 형성하였으며, 다양한 크기의 솔더 범프를 간단한 방법으로 형성하였다. 또한 무전해 니켈/솔더 계면 반응과 Bump shear test를 통한 기계적 성질을 고찰하는 한편, 계면 반응 결과는 스크린 프린팅에 의해 형성된 솔더 범프의 결과와 비교함으로써, 저가의 공정으로 미세 피치를 갖는 솔더 범프를 형성할 수 있는 Solder droplet jetting 방법이 기존의 방법에 의해 형성된 솔더 범프의 특성과 유사함을 고찰하였다. 마지막으로 실제 칩에 적용 되는 솔더 범프를 형성하여 플립칩 어셈블리 및 전기적 테스트를 수행하여, Solder droplet jetting이 실제 차세대 플립칩용 솔더 범프 형성 방법으로서 적용될 수 있음을 고찰하였다.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.