• Korean Journal of Materials Research
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• v.9 no.1
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• pp.104-107
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• 1999

We investigated the effects of cooling condition on deep levels and iron precipitate formation in iron-contaminated p-type silicon by DLTS(Deep Level Transient Spectroscopy) and preferential etching technique. Dependency of cooling condition on Bulk Micro-Defect (BMD) and four different iron-related deep traps were observed. For normal cooling condition, T1, T2, T3, T4 traps that related to Fe\ulcorner or Fe-O complex were obtained. However, the trap with activation energy, 0.4 eV was observed for slow cooling condition. The trap caused by the $\textrm{Fe}^{+}\textrm{}^{-}$ pair (H4:0.56eV) were detected only at the case of $\textrm{LN}_{2}$ quenching condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.497-500
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• 2001

Due to their better photosensitivity in X-ray, the amorphous selenium based photoreceptor is widely used on the X-ray conversion materials. It was possible to control the charge carrier transport of amorphous selenium by suitably alloying a-Se with other elements(e,g. As, Cl). The charge transport properties of amorphous Selenium is decided on hole which is induced from metal to selenium in metal-selenium junction and which is transferred in a-Se bulk. This phenomenon is resulted of changing electric field owing to increasing of space charge by deep trap of a-Se bulk. In this paper, We dopped the chlorine to compensate deep hole trap and deposited blocking layer using dielectric material to prevent from increasing space charge for injection charge between metal electrode and a-Se layer. We compared space charge and the decreasing of trap density through measuring dark and photo current.

• Journal of Sensor Science and Technology
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• v.27 no.3
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.497-500
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• 2001

Due to their better photosensitivity in X-ray, the amorphous selenium based photoreceptor is widely used on the X-ray conversion materials. It was possible to control the charge carrier transport of amorphous selenium by suitably alloying a-Se with other elements(e.g. As, Cl). The charge transport properties of amorphous Selenium is decided on hole which is induced from metal to selenium in metal-selenium junction and which is transferred in a-Se bulk. This phenomenon is resulted of changing electric field owing to increasing of space charge by deep trap of a-Se bulk. In this paper, We dopped the chlorine to compensate deep hole trap and deposited blocking layer using dielectric material to prevent from increasing space charge for injection charge between metal electrode and a-Se layer. We compared space charge and the decreasing of trap density through measuring dark and photo current. 缀Ѐ㘰〻ሀ䝥湥牡氠瑥捨湯汯杹

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Journal of the Korean Ceramic Society
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• v.31 no.5
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• pp.529-537
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• 1994

The principle of the Isothermal Capacitance Transient Spectroscopy[ICTS] were explained to measure the electronic trap levels in oxide ceramics. The measurement apparatus and the theory of the ICTS were described in detail. The trap energy evaluation was performed for the ZnO varistor and BaTiO3 ceramics. The grain boundary interface trap levels were detected at -5$0^{\circ}C$~6$0^{\circ}C$ in the case of ZnO varistor and PTCR samples, and the bulk trap levels were detected at 2$0^{\circ}C$~60~ in BaTiO3. The trap energy levels of the above samples could be directly determined by ICTS measurement.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.996-1000
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.58-62
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• 1995

Thermally stimulated currents have been measured to investigate the trap characteristics of the MONOS structures with the tunneling oxide layer of 27${\AA}$ thick nitride layer of 73${\AA}$ thick and blocking oxide layer of 40${\AA}$ thick. By changing the write-in voltage and the write-in temperature, peaks of the I-T characteristic curve due to the nitride bulk traps and the blocking oxide-nitride interface traps ware separated from each other experimentally. The results indicate that the nitride bulk traps are distributed spatially at a single energy level and the blocking oxide-nitride interface traps are distributed energetically at interface.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.