• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1850-1851
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• 전기학회논문지
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• 제56권5호
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• pp.980-986
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• 2007

Boundary scan test structure(JTAG IEEE 1149.1 standard) that supports an internal scan chain is generally being used to test CUT(circuit under test). Since the internal scan chain can only have a single scan-in port and a single scan-out port; however, existing boundary test methods can not be used when multiple scan chains are present in CUT. Those chains must be stitched to form a single scan chain as shown in this paper. We propose an efficient boundary scan test structure that adds a circuit called Clock Group Register(CGR) for multiple clocks testing within the design of multiple scan chains. The proposed CGR has the function of grouping clocks. By adding CGR to a previously existing boundary scan design, the design is modified. This revised scan design overcomes the limitation of supporting a single scan-in port and out port, and it bolsters multiple scan-in ports and out ports. Through our experiments, the effectiveness of CGR is proved. With this, it is possible to test more complicated designs that have high density with a little effort. Furthermore, it will also benefit in designing those complicated circuits.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1840-1841
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.115-121
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• 2004

본 논문에서 구현한 GenJTAG은 웹기반 경계 주사 회로 자동 생성기이다. GenJTAG은 경계 주사 기법의 공개 명령어를 모두 지원하고 다른 테스트 용이화 기법을 위한 특수 명령어를 지원할 수 있는 경계 주사 회로를 생성하여 준다. 생성된 경계주사 회로는 행위 수준 verilog-HDL 코드로 기술되므로 요구 사항이 변경될 경우 사용자가 용이하게 수정할 수 있다. 특히, GenJTAG은 웹을 통하여 사용할 수 있으므로 누구나 쉽게 경계 주사 회로를 생성할 수 있는 이점이 있다.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권11호
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• 한국멀티미디어학회논문지
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• 제4권6호
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• pp.570-578
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• 2001

경계 주사 구조(Boundary Scan Architecture)기 법은 복잡한 인쇄 회로 기판(PCB : Printed Circuit Board)을 테스트하기 위해 도입되었다. 이러한 경계 주사 구조는 시스템의 정상 동작에 간섭을 주지 않고 시스템의 동작 상태를 실시간 모니터링 하는데 대단한 잠재력을 지니고 있다. 본 논문에서는 경계 주사 구조를 이용하여 시스템의 작동 상태를 실시간으로 모니터 하기 위한 새로운 실장 제어기를 제안하고 설계한다. 제안된 실시간 모니터링 실장 제어기는 경계 주사 구조의 경계 주사 셀 제어기(Test Access Port Controller)와 범용 실장 제어기(Embedded Controller)로 구성되어 있다. 제안된 경계 주사 구조를 이용한 실시간 모니터링 실장제어기는 하드와이어의 자원을 절약해 주고 경계 주사 구조를 지니고 있는 칩에 쉽게 인터페이스 된다. 실험 결과는 제안된 실장제어 기가 시스템의 동작 상태를 실시간 모니터 하는데 호스트 컴퓨터에 의한 모니터 링에 비해 효과적임을 보여준다.

• 전자공학회논문지
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• 제52권6호
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• pp.70-76
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• 2015

본 논문은 FPGA 내부의 경계 스캔 체인을 자가 테스트 회로로써 재활용하기 위한 FPGA 자가 테스트 회로 설계 기술을 소개한다. FPGA의 경계 스캔 체인은 테스트나 디버깅 기능뿐만 아니라 각 셀에 연결되어 있는 입출력 핀의 기능을 설정하기 위해서도 사용되기 때문에 일반적인 칩의 경계 스캔 셀보다 매우 크다. 따라서, 본 논문에서는 FPGA 경계 스캔 셀의 구조를 분석하고 소수의 FPGA 로직과 함께 테스트 패턴 생성과 결과 분석이 가능하도록 설계한 BIST(built-in-self-test) 회로를 제시한다. FPGA의 경계 스캔 체인을 자가 테스트를 위하여 재사용함으로써 면적 오버헤드를 줄일 수 있고 보드상에서 프로세서를 사용한 온-라인(on-line) 테스트/모니터링도 가능하다. 실험을 통하여 오버헤드 증가량과 시뮬레이션 결과를 제시한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.669-671
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• 1998

Due to the serial nature of scan chains, the use of the boundary scan chain leads the high application costs. And with 3-state net, it is important to avoid enabling the two drivers in a net. In this paper, the new test method for 3-state nets in the multiple boundary scan chains is presented. This method configures the boundary scan cells as multiple scan chains and the test application time can be reduced. Also three efficient algorithms are proposed for testing the interconnects in a board without the collision of the test data in 3-state nets.

• 전자공학회논문지A
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• 제31A권6호
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.